From f447ed2dbc844d645ef8bf82cc04281fa4163aed Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 17 Oct 2012 19:46:49 -0500 Subject: [PATCH 01/11] zynq: use GIC device tree bindings The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode register addresses. Signed-off-by: Josh Cartwright Cc: John Linn Acked-by: Arnd Bergmann Tested-by: Michal Simek --- arch/arm/boot/dts/zynq-ep107.dts | 10 ++++++---- arch/arm/mach-zynq/common.c | 7 ++++++- arch/arm/mach-zynq/include/mach/zynq_soc.h | 2 -- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts index 37ca192fb193..f9140901e8ef 100644 --- a/arch/arm/boot/dts/zynq-ep107.dts +++ b/arch/arm/boot/dts/zynq-ep107.dts @@ -36,16 +36,18 @@ amba { ranges; intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; interrupt-controller; - compatible = "arm,gic"; - reg = <0xF8F01000 0x1000>; - #interrupt-cells = <2>; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; }; uart0: uart@e0000000 { compatible = "xlnx,xuartps"; reg = <0xE0000000 0x1000>; - interrupts = <59 0>; + interrupts = <0 27 4>; clock = <50000000>; }; }; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index ab5cfddc0d7b..d73963b422af 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -55,12 +55,17 @@ static void __init xilinx_init_machine(void) of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } +static struct of_device_id irq_match[] __initdata = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + { } +}; + /** * xilinx_irq_init() - Interrupt controller initialization for the GIC. */ static void __init xilinx_irq_init(void) { - gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); + of_irq_init(irq_match); } /* The minimum devices needed to be mapped before the VM system is up and diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h index d0d3f8fb06dd..3d1c6a6a8feb 100644 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -35,8 +35,6 @@ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) -#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) #define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) /* From 0fcfdbcacf6fa234064126e5b18c720ca27bc6e7 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Tue, 23 Oct 2012 17:34:22 -0500 Subject: [PATCH 02/11] zynq: use pl310 device tree bindings The Zynq has a PL310 L2 cache controller. Convert in-tree uses to using the device tree. Signed-off-by: Josh Cartwright Cc: John Linn Acked-by: Arnd Bergmann Tested-by: Michal Simek --- arch/arm/boot/dts/zynq-ep107.dts | 9 +++++++++ arch/arm/mach-zynq/common.c | 9 +-------- arch/arm/mach-zynq/include/mach/zynq_soc.h | 4 ---- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts index f9140901e8ef..574bc044f572 100644 --- a/arch/arm/boot/dts/zynq-ep107.dts +++ b/arch/arm/boot/dts/zynq-ep107.dts @@ -44,6 +44,15 @@ intc: interrupt-controller@f8f01000 { <0xF8F00100 0x100>; }; + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + arm,data-latency = <2 3 2>; + arm,tag-latency = <2 3 2>; + cache-unified; + cache-level = <2>; + }; + uart0: uart@e0000000 { compatible = "xlnx,xuartps"; reg = <0xE0000000 0x1000>; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index d73963b422af..056091a5a417 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -45,12 +45,10 @@ static struct of_device_id zynq_of_bus_ids[] __initdata = { */ static void __init xilinx_init_machine(void) { -#ifdef CONFIG_CACHE_L2X0 /* * 64KB way size, 8-way associativity, parity disabled */ - l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF); -#endif + l2x0_of_init(0x02060000, 0xF0F0FFFF); of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } @@ -83,11 +81,6 @@ static struct map_desc io_desc[] __initdata = { .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), .length = SZ_8K, .type = MT_DEVICE, - }, { - .virtual = PL310_L2CC_VIRT, - .pfn = __phys_to_pfn(PL310_L2CC_PHYS), - .length = SZ_4K, - .type = MT_DEVICE, }, #ifdef CONFIG_DEBUG_LL diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h index 3d1c6a6a8feb..218283a94247 100644 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -25,9 +25,6 @@ #define TTC0_PHYS 0xF8001000 #define TTC0_VIRT TTC0_PHYS -#define PL310_L2CC_PHYS 0xF8F02000 -#define PL310_L2CC_VIRT PL310_L2CC_PHYS - #define SCU_PERIPH_PHYS 0xF8F00000 #define SCU_PERIPH_VIRT SCU_PERIPH_PHYS @@ -35,7 +32,6 @@ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) /* * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical From f7977939e956bdf6558ae6f4b743653db9f5c291 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 24 Oct 2012 15:04:07 -0500 Subject: [PATCH 03/11] zynq: remove use of CLKDEV_LOOKUP The Zynq support in mainline does not (yet) make use of any of the generic clk or clk lookup functionality. Remove what is upstream for now, until the out-of-tree implementation is in suitable form for merging. An important side effect of this patch is that it allows the building of a Zynq kernel without running into unresolved symbol problems: drivers/built-in.o: In function `amba_get_enable_pclk': clkdev.c:(.text+0x444): undefined reference to `clk_enable' drivers/built-in.o: In function `amba_remove': clkdev.c:(.text+0x488): undefined reference to `clk_disable' drivers/built-in.o: In function `amba_probe': clkdev.c:(.text+0x540): undefined reference to `clk_disable' drivers/built-in.o: In function `amba_device_add': clkdev.c:(.text+0x77c): undefined reference to `clk_disable' drivers/built-in.o: In function `enable_clock': clkdev.c:(.text+0x29738): undefined reference to `clk_enable' drivers/built-in.o: In function `disable_clock': clkdev.c:(.text+0x29778): undefined reference to `clk_disable' drivers/built-in.o: In function `__pm_clk_remove': clkdev.c:(.text+0x297f8): undefined reference to `clk_disable' drivers/built-in.o: In function `pm_clk_suspend': clkdev.c:(.text+0x29bc8): undefined reference to `clk_disable' drivers/built-in.o: In function `pm_clk_resume': clkdev.c:(.text+0x29c28): undefined reference to `clk_enable' make[2]: *** [vmlinux] Error 1 make[1]: *** [sub-make] Error 2 make: *** [all] Error 2 In addition, eliminate Zynq's "use" of the versatile platform, as it is no longer needed. As Nick Bowler points out: For the record, I think this was introduced by commit 56a34b03ff427 ("ARM: versatile: Make plat-versatile clock optional") which forgot to select PLAT_VERSATILE_CLOCK on Zynq. This is not all that surprising, because the fact that Zynq "uses" PLAT_VERSATILE is secretly hidden in the Makefile. Nevertheless, the only feature from versatile that Zynq needed was the clock support, so this patch should *also* delete the secret use of plat-versatile by removing this line from arch/arm/Makefile: plat-$(CONFIG_ARCH_ZYNQ) += versatile Signed-off-by: Josh Cartwright Cc: John Linn Acked-by: Arnd Bergmann Tested-by: Michal Simek --- arch/arm/Kconfig | 1 - arch/arm/Makefile | 1 - arch/arm/mach-zynq/common.c | 1 - arch/arm/mach-zynq/include/mach/clkdev.h | 32 ------------------------ 4 files changed, 35 deletions(-) delete mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ade7e924bef5..21ed87bc3503 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -959,7 +959,6 @@ config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" select ARM_AMBA select ARM_GIC - select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS select ICST diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5f914fca911b..554cfac41429 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -199,7 +199,6 @@ machine-$(CONFIG_ARCH_ZYNQ) += zynq plat-$(CONFIG_ARCH_MXC) += mxc plat-$(CONFIG_ARCH_OMAP) += omap plat-$(CONFIG_ARCH_S3C64XX) += samsung -plat-$(CONFIG_ARCH_ZYNQ) += versatile plat-$(CONFIG_PLAT_IOP) += iop plat-$(CONFIG_PLAT_NOMADIK) += nomadik plat-$(CONFIG_PLAT_ORION) += orion diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 056091a5a417..ba48f067d8f2 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -31,7 +31,6 @@ #include #include -#include #include "common.h" static struct of_device_id zynq_of_bus_ids[] __initdata = { diff --git a/arch/arm/mach-zynq/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/clkdev.h deleted file mode 100644 index c6e73d81a459..000000000000 --- a/arch/arm/mach-zynq/include/mach/clkdev.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-zynq/include/mach/clkdev.h - * - * Copyright (C) 2011 Xilinx, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#include - -struct clk { - unsigned long rate; - const struct clk_ops *ops; - const struct icst_params *params; - void __iomem *vcoreg; -}; - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif From f58007762f537ba13674a3138b3f4c20fff1cba9 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Sun, 21 Oct 2012 21:15:37 -0500 Subject: [PATCH 04/11] zynq: move static peripheral mappings Shifting them up into the vmalloc region prevents the following warning, when booting a zynq qemu target with more than 512mb of RAM: BUG: mapping for 0xe0000000 at 0xe0000000 out of vmalloc space In addition, it allows for reuse of these mappings when the proper drivers issue requests via ioremap(). There are currently unknown issues with the early uart mapping. For now, the uart will be mapped to a known working address. Signed-off-by: Josh Cartwright Cc: John Linn Acked-by: Arnd Bergmann Tested-by: Michal Simek --- arch/arm/mach-zynq/common.c | 6 +++--- arch/arm/mach-zynq/include/mach/zynq_soc.h | 25 +++++++++++++--------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index ba48f067d8f2..ba8d14f78d4d 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -73,12 +73,12 @@ static struct map_desc io_desc[] __initdata = { { .virtual = TTC0_VIRT, .pfn = __phys_to_pfn(TTC0_PHYS), - .length = SZ_4K, + .length = TTC0_SIZE, .type = MT_DEVICE, }, { .virtual = SCU_PERIPH_VIRT, .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), - .length = SZ_8K, + .length = SCU_PERIPH_SIZE, .type = MT_DEVICE, }, @@ -86,7 +86,7 @@ static struct map_desc io_desc[] __initdata = { { .virtual = UART0_VIRT, .pfn = __phys_to_pfn(UART0_PHYS), - .length = SZ_4K, + .length = UART0_SIZE, .type = MT_DEVICE, }, #endif diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h index 218283a94247..1b8bf0ecbcb0 100644 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -15,27 +15,32 @@ #ifndef __MACH_XILINX_SOC_H__ #define __MACH_XILINX_SOC_H__ +#include + #define PERIPHERAL_CLOCK_RATE 2500000 -/* For now, all mappings are flat (physical = virtual) +/* Static peripheral mappings are mapped at the top of the vmalloc region. The + * early uart mapping causes intermediate problems/failure at certain + * addresses, including the very top of the vmalloc region. Map it at an + * address that is known to work. */ -#define UART0_PHYS 0xE0000000 -#define UART0_VIRT UART0_PHYS +#define UART0_PHYS 0xE0000000 +#define UART0_SIZE SZ_4K +#define UART0_VIRT 0xF0001000 -#define TTC0_PHYS 0xF8001000 -#define TTC0_VIRT TTC0_PHYS +#define TTC0_PHYS 0xF8001000 +#define TTC0_SIZE SZ_4K +#define TTC0_VIRT (VMALLOC_END - TTC0_SIZE) -#define SCU_PERIPH_PHYS 0xF8F00000 -#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS +#define SCU_PERIPH_PHYS 0xF8F00000 +#define SCU_PERIPH_SIZE SZ_8K +#define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE) /* The following are intended for the devices that are mapped early */ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -/* - * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical - */ #define LL_UART_PADDR UART0_PHYS #define LL_UART_VADDR UART0_VIRT From 03e07595febc4857b2b6ad756826f369c7628ec8 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 31 Oct 2012 11:11:59 -0600 Subject: [PATCH 05/11] ARM: zynq: move arm-specific sys_timer out of ttc Move the sys_timer definition out of ttc driver and make it part of the common zynq code. This is preparation for renaming and COMMON_CLK support. Signed-off-by: Josh Cartwright Tested-by: Michal Simek --- arch/arm/mach-zynq/common.c | 13 +++++++++++++ arch/arm/mach-zynq/common.h | 4 +--- arch/arm/mach-zynq/timer.c | 10 +--------- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index ba8d14f78d4d..6f058258b491 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -93,6 +94,18 @@ static struct map_desc io_desc[] __initdata = { }; +static void __init xilinx_zynq_timer_init(void) +{ + xttcpss_timer_init(); +} + +/* + * Instantiate and initialize the system timer structure + */ +static struct sys_timer xttcpss_sys_timer = { + .init = xilinx_zynq_timer_init, +}; + /** * xilinx_map_io() - Create memory mappings needed for early I/O. */ diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index a009644a1555..954b91c13c91 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,8 +17,6 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ -#include - -extern struct sys_timer xttcpss_sys_timer; +void __init xttcpss_timer_init(void); #endif diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index c2c96cc7d6e7..c93cbe55a495 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -24,7 +24,6 @@ #include #include -#include #include #include "common.h" @@ -269,7 +268,7 @@ static struct clock_event_device xttcpss_clockevent = { * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework **/ -static void __init xttcpss_timer_init(void) +void __init xttcpss_timer_init(void) { xttcpss_timer_hardware_init(); clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); @@ -289,10 +288,3 @@ static void __init xttcpss_timer_init(void) xttcpss_clockevent.cpumask = cpumask_of(0); clockevents_register_device(&xttcpss_clockevent); } - -/* - * Instantiate and initialize the system timer structure - */ -struct sys_timer xttcpss_sys_timer = { - .init = xttcpss_timer_init, -}; From 78d6785db13572f22d287d8c1739ceb4edf54bdc Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 31 Oct 2012 13:45:17 -0600 Subject: [PATCH 06/11] ARM: zynq: dts: add description of the second uart The zynq-7000 has an additional UART at 0xE0001000. Describe it in the device tree. Signed-off-by: Josh Cartwright Acked-by: Michal Simek --- arch/arm/boot/dts/zynq-ep107.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts index 574bc044f572..5caf10011f59 100644 --- a/arch/arm/boot/dts/zynq-ep107.dts +++ b/arch/arm/boot/dts/zynq-ep107.dts @@ -59,5 +59,12 @@ uart0: uart@e0000000 { interrupts = <0 27 4>; clock = <50000000>; }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + clock = <50000000>; + }; }; }; From aaf5e0be79e37d5a8509f09852788fa6a82522b2 Mon Sep 17 00:00:00 2001 From: Nick Bowler Date: Mon, 5 Nov 2012 16:45:49 -0500 Subject: [PATCH 07/11] ARM: zynq: Allow UART1 to be used as DEBUG_LL console. The main UART on the Xilinx ZC702 board is UART1, located at address e0001000. Add a Kconfig option to select this device as the low-level debugging port. This allows the really early boot printouts to reach the USB serial adaptor on this board. For consistency's sake, add a choice entry for UART0 even though it is the the default if UART1 is not selected. Signed-off-by: Nick Bowler Tested-by: Josh Cartwright Acked-by: Michal Simek --- arch/arm/Kconfig.debug | 17 +++++++++++++++++ arch/arm/mach-zynq/common.c | 6 +++--- arch/arm/mach-zynq/include/mach/zynq_soc.h | 16 +++++++++++----- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index b0f3857b3a4c..7754d51f2b19 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -132,6 +132,23 @@ choice their output to UART1 serial port on DaVinci TNETV107X devices. + config DEBUG_ZYNQ_UART0 + bool "Kernel low-level debugging on Xilinx Zynq using UART0" + depends on ARCH_ZYNQ + help + Say Y here if you want the debug print routines to direct + their output to UART0 on the Zynq platform. + + config DEBUG_ZYNQ_UART1 + bool "Kernel low-level debugging on Xilinx Zynq using UART1" + depends on ARCH_ZYNQ + help + Say Y here if you want the debug print routines to direct + their output to UART1 on the Zynq platform. + + If you have a ZC702 board and want early boot messages to + appear on the USB serial adaptor, select this option. + config DEBUG_DC21285_PORT bool "Kernel low-level debugging messages via footbridge serial port" depends on FOOTBRIDGE diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 6f058258b491..f0eef848c0d0 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -85,9 +85,9 @@ static struct map_desc io_desc[] __initdata = { #ifdef CONFIG_DEBUG_LL { - .virtual = UART0_VIRT, - .pfn = __phys_to_pfn(UART0_PHYS), - .length = UART0_SIZE, + .virtual = LL_UART_VADDR, + .pfn = __phys_to_pfn(LL_UART_PADDR), + .length = UART_SIZE, .type = MT_DEVICE, }, #endif diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h index 1b8bf0ecbcb0..5ebbd8e6eeee 100644 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -25,8 +25,9 @@ * address that is known to work. */ #define UART0_PHYS 0xE0000000 -#define UART0_SIZE SZ_4K -#define UART0_VIRT 0xF0001000 +#define UART1_PHYS 0xE0001000 +#define UART_SIZE SZ_4K +#define UART_VIRT 0xF0001000 #define TTC0_PHYS 0xF8001000 #define TTC0_SIZE SZ_4K @@ -36,12 +37,17 @@ #define SCU_PERIPH_SIZE SZ_8K #define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE) +#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1) +# define LL_UART_PADDR UART1_PHYS +#else +# define LL_UART_PADDR UART0_PHYS +#endif + +#define LL_UART_VADDR UART_VIRT + /* The following are intended for the devices that are mapped early */ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define LL_UART_PADDR UART0_PHYS -#define LL_UART_VADDR UART0_VIRT - #endif From e06f1a9ed7ebff170ba05d2606d079fb36c6a52d Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 31 Oct 2012 12:24:48 -0600 Subject: [PATCH 08/11] ARM: zynq: dts: split up device tree The purpose of the created zynq-7000.dtsi file is to describe the hardware common to all Zynq 7000-based boards. Also, get rid of the zynq-ep107 device tree, since it is not hardware anyone can purchase. Add a zc702 dts file based on the zynq-7000.dtsi. Add it to the dts/Makefile so it is built with the 'dtbs' target. Signed-off-by: Josh Cartwright Acked-by: Michal Simek --- arch/arm/boot/dts/Makefile | 1 + .../dts/{zynq-ep107.dts => zynq-7000.dtsi} | 19 ++---------- arch/arm/boot/dts/zynq-zc702.dts | 30 +++++++++++++++++++ arch/arm/mach-zynq/common.c | 3 +- 4 files changed, 36 insertions(+), 17 deletions(-) rename arch/arm/boot/dts/{zynq-ep107.dts => zynq-7000.dtsi} (79%) create mode 100644 arch/arm/boot/dts/zynq-zc702.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f37cf9fa5fa0..76ed11e68f72 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -103,5 +103,6 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ wm8505-ref.dtb \ wm8650-mid.dtb +dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb endif diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-7000.dtsi similarity index 79% rename from arch/arm/boot/dts/zynq-ep107.dts rename to arch/arm/boot/dts/zynq-7000.dtsi index 5caf10011f59..8b30e596deab 100644 --- a/arch/arm/boot/dts/zynq-ep107.dts +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -10,29 +10,16 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +/include/ "skeleton.dtsi" -/dts-v1/; / { - model = "Xilinx Zynq EP107"; - compatible = "xlnx,zynq-ep107"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - memory { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - chosen { - bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk"; - linux,stdout-path = &uart0; - }; + compatible = "xlnx,zynq-7000"; amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + interrupt-parent = <&intc>; ranges; intc: interrupt-controller@f8f01000 { diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts new file mode 100644 index 000000000000..e25a307438ad --- /dev/null +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2011 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq ZC702 Development Board"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS1,115200 earlyprintk"; + }; + +}; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index f0eef848c0d0..5441323e2a68 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -115,7 +115,8 @@ static void __init xilinx_map_io(void) } static const char *xilinx_dt_match[] = { - "xlnx,zynq-ep107", + "xlnx,zynq-zc702", + "xlnx,zynq-7000", NULL }; From 45aa2c27ada4829bc91bd80455bc67059ac06bc5 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Tue, 13 Nov 2012 17:26:48 -0600 Subject: [PATCH 09/11] clk: Add support for fundamental zynq clks Provide simplified models for the necessary clocks on the zynq-7000 platform. Currently, the PLLs, the CPU clock network, and the basic peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled. OF bindings are also provided and documented. Signed-off-by: Josh Cartwright Signed-off-by: Soren Brinkmann Acked-by: Mike Turquette Acked-by: Michal Simek --- .../devicetree/bindings/clock/zynq-7000.txt | 55 +++ drivers/clk/clk-zynq.c | 383 ++++++++++++++++++ include/linux/clk/zynq.h | 24 ++ 3 files changed, 462 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/zynq-7000.txt create mode 100644 drivers/clk/clk-zynq.c create mode 100644 include/linux/clk/zynq.h diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt new file mode 100644 index 000000000000..23ae1db1bc13 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt @@ -0,0 +1,55 @@ +Device Tree Clock bindings for the Zynq 7000 EPP + +The Zynq EPP has several different clk providers, each with there own bindings. +The purpose of this document is to document their usage. + +See clock_bindings.txt for more information on the generic clock bindings. +See Chapter 25 of Zynq TRM for more information about Zynq clocks. + +== PLLs == + +Used to describe the ARM_PLL, DDR_PLL, and IO_PLL. + +Required properties: +- #clock-cells : shall be 0 (only one clock is output from this node) +- compatible : "xlnx,zynq-pll" +- reg : pair of u32 values, which are the address offsets within the SLCR + of the relevant PLL_CTRL register and PLL_CFG register respectively +- clocks : phandle for parent clock. should be the phandle for ps_clk + +Optional properties: +- clock-output-names : name of the output clock + +Example: + armpll: armpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x100 0x110>; + clock-output-names = "armpll"; + }; + +== Peripheral clocks == + +Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks. + +Required properties: +- #clock-cells : shall be 1 +- compatible : "xlnx,zynq-periph-clock" +- reg : a single u32 value, describing the offset within the SLCR where + the CLK_CTRL register is found for this peripheral +- clocks : phandle for parent clocks. should hold phandles for + the IO_PLL, ARM_PLL, and DDR_PLL in order +- clock-output-names : names of the output clock(s). For peripherals that have + two output clocks (for example, the UART), two clocks + should be listed. + +Example: + uart_clk: uart_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-periph-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x154>; + clock-output-names = "uart0_ref_clk", + "uart1_ref_clk"; + }; diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c new file mode 100644 index 000000000000..37a30514fd66 --- /dev/null +++ b/drivers/clk/clk-zynq.c @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2012 National Instruments + * + * Josh Cartwright + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ +#include +#include +#include +#include +#include + +static void __iomem *slcr_base; + +struct zynq_pll_clk { + struct clk_hw hw; + void __iomem *pll_ctrl; + void __iomem *pll_cfg; +}; + +#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw) + +#define CTRL_PLL_FDIV(x) ((x) >> 12) + +static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_pll_clk *pll = to_zynq_pll_clk(hw); + return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl)); +} + +static const struct clk_ops zynq_pll_clk_ops = { + .recalc_rate = zynq_pll_recalc_rate, +}; + +static void __init zynq_pll_clk_setup(struct device_node *np) +{ + struct clk_init_data init; + struct zynq_pll_clk *pll; + const char *parent_name; + struct clk *clk; + u32 regs[2]; + int ret; + + ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs)); + if (WARN_ON(ret)) + return; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (WARN_ON(!pll)) + return; + + pll->pll_ctrl = slcr_base + regs[0]; + pll->pll_cfg = slcr_base + regs[1]; + + of_property_read_string(np, "clock-output-names", &init.name); + + init.ops = &zynq_pll_clk_ops; + parent_name = of_clk_get_parent_name(np, 0); + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(ret)) + return; +} + +struct zynq_periph_clk { + struct clk_hw hw; + struct clk_onecell_data onecell_data; + struct clk *gates[2]; + void __iomem *clk_ctrl; + spinlock_t clkact_lock; +}; + +#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw) + +static const u8 periph_clk_parent_map[] = { + 0, 0, 1, 2 +}; +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4]) +#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) + +static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); + return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl)); +} + +static u8 zynq_periph_get_parent(struct clk_hw *hw) +{ + struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); + return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl)); +} + +static const struct clk_ops zynq_periph_clk_ops = { + .recalc_rate = zynq_periph_recalc_rate, + .get_parent = zynq_periph_get_parent, +}; + +static void __init zynq_periph_clk_setup(struct device_node *np) +{ + struct zynq_periph_clk *periph; + const char *parent_names[3]; + struct clk_init_data init; + int clk_num = 0, err; + const char *name; + struct clk *clk; + u32 reg; + int i; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + periph = kzalloc(sizeof(*periph), GFP_KERNEL); + if (WARN_ON(!periph)) + return; + + periph->clk_ctrl = slcr_base + reg; + spin_lock_init(&periph->clkact_lock); + + init.name = np->name; + init.ops = &zynq_periph_clk_ops; + for (i = 0; i < ARRAY_SIZE(parent_names); i++) + parent_names[i] = of_clk_get_parent_name(np, i); + init.parent_names = parent_names; + init.num_parents = ARRAY_SIZE(parent_names); + + periph->hw.init = &init; + + clk = clk_register(NULL, &periph->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + err = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(err)) + return; + + err = of_property_read_string_index(np, "clock-output-names", 0, + &name); + if (WARN_ON(err)) + return; + + periph->gates[0] = clk_register_gate(NULL, name, np->name, 0, + periph->clk_ctrl, 0, 0, + &periph->clkact_lock); + if (WARN_ON(IS_ERR(periph->gates[0]))) + return; + clk_num++; + + /* some periph clks have 2 downstream gates */ + err = of_property_read_string_index(np, "clock-output-names", 1, + &name); + if (err != -ENODATA) { + periph->gates[1] = clk_register_gate(NULL, name, np->name, 0, + periph->clk_ctrl, 1, 0, + &periph->clkact_lock); + if (WARN_ON(IS_ERR(periph->gates[1]))) + return; + clk_num++; + } + + periph->onecell_data.clks = periph->gates; + periph->onecell_data.clk_num = clk_num; + + err = of_clk_add_provider(np, of_clk_src_onecell_get, + &periph->onecell_data); + if (WARN_ON(err)) + return; +} + +/* CPU Clock domain is modelled as a mux with 4 children subclks, whose + * derivative rates depend on CLK_621_TRUE + */ + +struct zynq_cpu_clk { + struct clk_hw hw; + struct clk_onecell_data onecell_data; + struct clk *subclks[4]; + void __iomem *clk_ctrl; + spinlock_t clkact_lock; +}; + +#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw) + +static const u8 zynq_cpu_clk_parent_map[] = { + 1, 1, 2, 0 +}; +#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)]) +#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) + +static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw) +{ + struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); + return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl)); +} + +static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); + return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl)); +} + +static const struct clk_ops zynq_cpu_clk_ops = { + .get_parent = zynq_cpu_clk_get_parent, + .recalc_rate = zynq_cpu_clk_recalc_rate, +}; + +struct zynq_cpu_subclk { + struct clk_hw hw; + void __iomem *clk_621; + enum { + CPU_SUBCLK_6X4X, + CPU_SUBCLK_3X2X, + CPU_SUBCLK_2X, + CPU_SUBCLK_1X, + } which; +}; + +#define CLK_621_TRUE(x) ((x) & 1) + +#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw); + +static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long uninitialized_var(rate); + struct zynq_cpu_subclk *subclk; + bool is_621; + + subclk = to_zynq_cpu_subclk(hw) + is_621 = CLK_621_TRUE(ioread32(subclk->clk_621)); + + switch (subclk->which) { + case CPU_SUBCLK_6X4X: + rate = parent_rate; + break; + case CPU_SUBCLK_3X2X: + rate = parent_rate / 2; + break; + case CPU_SUBCLK_2X: + rate = parent_rate / (is_621 ? 3 : 2); + break; + case CPU_SUBCLK_1X: + rate = parent_rate / (is_621 ? 6 : 4); + break; + }; + + return rate; +} + +static const struct clk_ops zynq_cpu_subclk_ops = { + .recalc_rate = zynq_cpu_subclk_recalc_rate, +}; + +static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which, + void __iomem *clk_621) +{ + struct zynq_cpu_subclk *subclk; + struct clk_init_data init; + struct clk *clk; + int err; + + err = of_property_read_string_index(np, "clock-output-names", + which, &init.name); + if (WARN_ON(err)) + goto err_read_output_name; + + subclk = kzalloc(sizeof(*subclk), GFP_KERNEL); + if (!subclk) + goto err_subclk_alloc; + + subclk->clk_621 = clk_621; + subclk->which = which; + + init.ops = &zynq_cpu_subclk_ops; + init.parent_names = &np->name; + init.num_parents = 1; + + subclk->hw.init = &init; + + clk = clk_register(NULL, &subclk->hw); + if (WARN_ON(IS_ERR(clk))) + goto err_clk_register; + + return clk; + +err_clk_register: + kfree(subclk); +err_subclk_alloc: +err_read_output_name: + return ERR_PTR(-EINVAL); +} + +static void __init zynq_cpu_clk_setup(struct device_node *np) +{ + struct zynq_cpu_clk *cpuclk; + const char *parent_names[3]; + struct clk_init_data init; + void __iomem *clk_621; + struct clk *clk; + u32 reg[2]; + int err; + int i; + + err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); + if (WARN_ON(err)) + return; + + cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); + if (WARN_ON(!cpuclk)) + return; + + cpuclk->clk_ctrl = slcr_base + reg[0]; + clk_621 = slcr_base + reg[1]; + spin_lock_init(&cpuclk->clkact_lock); + + init.name = np->name; + init.ops = &zynq_cpu_clk_ops; + for (i = 0; i < ARRAY_SIZE(parent_names); i++) + parent_names[i] = of_clk_get_parent_name(np, i); + init.parent_names = parent_names; + init.num_parents = ARRAY_SIZE(parent_names); + + cpuclk->hw.init = &init; + + clk = clk_register(NULL, &cpuclk->hw); + if (WARN_ON(IS_ERR(clk))) + return; + + err = of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (WARN_ON(err)) + return; + + for (i = 0; i < 4; i++) { + cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621); + if (WARN_ON(IS_ERR(cpuclk->subclks[i]))) + return; + } + + cpuclk->onecell_data.clks = cpuclk->subclks; + cpuclk->onecell_data.clk_num = i; + + err = of_clk_add_provider(np, of_clk_src_onecell_get, + &cpuclk->onecell_data); + if (WARN_ON(err)) + return; +} + +static const __initconst struct of_device_id zynq_clk_match[] = { + { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, + { .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, }, + { .compatible = "xlnx,zynq-periph-clock", + .data = zynq_periph_clk_setup, }, + { .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, }, + {} +}; + +void __init xilinx_zynq_clocks_init(void __iomem *slcr) +{ + slcr_base = slcr; + of_clk_init(zynq_clk_match); +} diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h new file mode 100644 index 000000000000..56be7cd9aa8b --- /dev/null +++ b/include/linux/clk/zynq.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2012 National Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_CLK_ZYNQ_H_ +#define __LINUX_CLK_ZYNQ_H_ + +void __init xilinx_zynq_clocks_init(void __iomem *slcr); + +#endif From 0f586fbf6f6a9119392a5cb0f193ac11c753b09e Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Thu, 8 Nov 2012 12:04:26 -0600 Subject: [PATCH 10/11] ARM: zynq: use zynq clk bindings Make the Zynq platform use the newly created zynq clk bindings. Signed-off-by: Josh Cartwright Acked-by: Michal Simek --- arch/arm/Kconfig | 1 + arch/arm/boot/dts/zynq-7000.dtsi | 56 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/zynq-zc702.dts | 4 +++ arch/arm/mach-zynq/common.c | 11 +++++++ drivers/clk/Makefile | 1 + 5 files changed, 73 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21ed87bc3503..ccfe0ab8c877 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -959,6 +959,7 @@ config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" select ARM_AMBA select ARM_GIC + select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS select ICST diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 8b30e596deab..bb3085ca4f06 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -53,5 +53,61 @@ uart1: uart@e0001000 { interrupts = <0 50 4>; clock = <50000000>; }; + + slcr: slcr@f8000000 { + compatible = "xlnx,zynq-slcr"; + reg = <0xF8000000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ps_clk: ps_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* clock-frequency set in board-specific file */ + clock-output-names = "ps_clk"; + }; + armpll: armpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x100 0x110>; + clock-output-names = "armpll"; + }; + ddrpll: ddrpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x104 0x114>; + clock-output-names = "ddrpll"; + }; + iopll: iopll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x108 0x118>; + clock-output-names = "iopll"; + }; + uart_clk: uart_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-periph-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x154>; + clock-output-names = "uart0_ref_clk", + "uart1_ref_clk"; + }; + cpu_clk: cpu_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-cpu-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x120 0x1C4>; + clock-output-names = "cpu_6x4x", + "cpu_3x2x", + "cpu_2x", + "cpu_1x"; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index e25a307438ad..86f44d5b0265 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -28,3 +28,7 @@ chosen { }; }; + +&ps_clk { + clock-frequency = <33333330>; +}; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 5441323e2a68..79bf5fb4dad3 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include #include @@ -96,6 +98,15 @@ static struct map_desc io_desc[] __initdata = { static void __init xilinx_zynq_timer_init(void) { + struct device_node *np; + void __iomem *slcr; + + np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); + slcr = of_iomap(np, 0); + WARN_ON(!slcr); + + xilinx_zynq_clocks_init(slcr); + xttcpss_timer_init(); } diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71a25b91de00..d35a34c58369 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -19,6 +19,7 @@ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o # Chip specific obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o From 91dc985c5e51af7036c1ccf9cea1b05662c96791 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Wed, 31 Oct 2012 13:56:14 -0600 Subject: [PATCH 11/11] ARM: zynq: add clk binding support to the ttc Add support for retrieving TTC configuration from device tree. This includes the ability to pull information about the driving clocks from the of_clk bindings. Signed-off-by: Josh Cartwright Acked-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 53 ++++++ arch/arm/boot/dts/zynq-zc702.dts | 10 ++ arch/arm/mach-zynq/timer.c | 279 ++++++++++++++++++------------- 3 files changed, 224 insertions(+), 118 deletions(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index bb3085ca4f06..401c1262d4ed 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -109,5 +109,58 @@ cpu_clk: cpu_clk { }; }; }; + + ttc0: ttc0@f8001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; + reg = <0xF8001000 0x1000>; + clocks = <&cpu_clk 3>; + clock-names = "cpu_1x"; + clock-ranges; + + ttc0_0: ttc0.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 10 4>; + }; + ttc0_1: ttc0.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 11 4>; + }; + ttc0_2: ttc0.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 12 4>; + }; + }; + + ttc1: ttc1@f8002000 { + #interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; + reg = <0xF8002000 0x1000>; + clocks = <&cpu_clk 3>; + clock-names = "cpu_1x"; + clock-ranges; + + ttc1_0: ttc1.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 37 4>; + }; + ttc1_1: ttc1.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 38 4>; + }; + ttc1_2: ttc1.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 39 4>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 86f44d5b0265..c772942a399a 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -32,3 +32,13 @@ chosen { &ps_clk { clock-frequency = <33333330>; }; + +&ttc0_0 { + status = "ok"; + compatible = "xlnx,ttc-counter-clocksource"; +}; + +&ttc0_1 { + status = "ok"; + compatible = "xlnx,ttc-counter-clockevent"; +}; diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index c93cbe55a495..9662306aa12f 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -23,31 +23,15 @@ #include #include #include +#include +#include +#include +#include +#include #include #include "common.h" -#define IRQ_TIMERCOUNTER0 42 - -/* - * This driver configures the 2 16-bit count-up timers as follows: - * - * T1: Timer 1, clocksource for generic timekeeping - * T2: Timer 2, clockevent source for hrtimers - * T3: Timer 3, - * - * The input frequency to the timer module for emulation is 2.5MHz which is - * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, - * the timers are clocked at 78.125KHz (12.8 us resolution). - * - * The input frequency to the timer module in silicon will be 200MHz. With the - * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution). - */ -#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */ -#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */ - -#define XTTCPSS_TIMER_BASE TTC0_BASE -#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1) /* * Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 @@ -64,9 +48,14 @@ #define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 -/* Setup the timers to use pre-scaling */ - -#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32) +/* Setup the timers to use pre-scaling, using a fixed value for now that will + * work across most input frequency, but it may need to be more dynamic + */ +#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ +#define PRESCALE 2048 /* The exponent must match this */ +#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) +#define CLK_CNTRL_PRESCALE_EN 1 +#define CNT_CNTRL_RESET (1<<4) /** * struct xttcpss_timer - This definition defines local timer structure @@ -74,11 +63,25 @@ * @base_addr: Base address of timer **/ struct xttcpss_timer { - void __iomem *base_addr; + void __iomem *base_addr; }; -static struct xttcpss_timer timers[2]; -static struct clock_event_device xttcpss_clockevent; +struct xttcpss_timer_clocksource { + struct xttcpss_timer xttc; + struct clocksource cs; +}; + +#define to_xttcpss_timer_clksrc(x) \ + container_of(x, struct xttcpss_timer_clocksource, cs) + +struct xttcpss_timer_clockevent { + struct xttcpss_timer xttc; + struct clock_event_device ce; + struct clk *clk; +}; + +#define to_xttcpss_timer_clkevent(x) \ + container_of(x, struct xttcpss_timer_clockevent, ce) /** * xttcpss_set_interval - Set the timer interval value @@ -100,7 +103,7 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer, /* Reset the counter (0x10) so that it starts from 0, one-shot mode makes this needed for timing to be right. */ - ctrl_reg |= 0x10; + ctrl_reg |= CNT_CNTRL_RESET; ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); } @@ -115,90 +118,31 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer, **/ static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = &xttcpss_clockevent; - struct xttcpss_timer *timer = dev_id; + struct xttcpss_timer_clockevent *xttce = dev_id; + struct xttcpss_timer *timer = &xttce->xttc; /* Acknowledge the interrupt and call event handler */ __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), timer->base_addr + XTTCPSS_ISR_OFFSET); - evt->event_handler(evt); + xttce->ce.event_handler(&xttce->ce); return IRQ_HANDLED; } -static struct irqaction event_timer_irq = { - .name = "xttcpss clockevent", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = xttcpss_clock_event_interrupt, -}; - /** - * xttcpss_timer_hardware_init - Initialize the timer hardware - * - * Initialize the hardware to start the clock source, get the clock - * event timer ready to use, and hook up the interrupt. - **/ -static void __init xttcpss_timer_hardware_init(void) -{ - /* Setup the clock source counter to be an incrementing counter - * with no interrupt and it rolls over at 0xFFFF. Pre-scale - it by 32 also. Let it start running now. - */ - timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE; - - __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_IER_OFFSET); - __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - - /* Setup the clock event timer to be an interval timer which - * is prescaled by 32 using the interval interrupt. Leave it - * disabled for now. - */ - - timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4; - - __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_IER_OFFSET); - - /* Setup IRQ the clock event timer */ - event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT]; - setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq); -} - -/** - * __raw_readl_cycles - Reads the timer counter register + * __xttc_clocksource_read - Reads the timer counter register * * returns: Current timer counter register value **/ -static cycle_t __raw_readl_cycles(struct clocksource *cs) +static cycle_t __xttc_clocksource_read(struct clocksource *cs) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE]; + struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc; return (cycle_t)__raw_readl(timer->base_addr + XTTCPSS_COUNT_VAL_OFFSET); } - -/* - * Instantiate and initialize the clock source structure - */ -static struct clocksource clocksource_xttcpss = { - .name = "xttcpss_timer1", - .rating = 200, /* Reasonable clock source */ - .read = __raw_readl_cycles, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - - /** * xttcpss_set_next_event - Sets the time interval for next event * @@ -210,7 +154,8 @@ static struct clocksource clocksource_xttcpss = { static int xttcpss_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt); + struct xttcpss_timer *timer = &xttce->xttc; xttcpss_set_interval(timer, cycles); return 0; @@ -225,12 +170,15 @@ static int xttcpss_set_next_event(unsigned long cycles, static void xttcpss_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt); + struct xttcpss_timer *timer = &xttce->xttc; u32 ctrl_reg; switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - xttcpss_set_interval(timer, TIMER_RATE / HZ); + xttcpss_set_interval(timer, + DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk), + PRESCALE * HZ)); break; case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: @@ -251,15 +199,106 @@ static void xttcpss_set_mode(enum clock_event_mode mode, } } -/* - * Instantiate and initialize the clock event structure - */ -static struct clock_event_device xttcpss_clockevent = { - .name = "xttcpss_timer2", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = xttcpss_set_next_event, - .set_mode = xttcpss_set_mode, - .rating = 200, +static void __init zynq_ttc_setup_clocksource(struct device_node *np, + void __iomem *base) +{ + struct xttcpss_timer_clocksource *ttccs; + struct clk *clk; + int err; + u32 reg; + + ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); + if (WARN_ON(!ttccs)) + return; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + clk = of_clk_get_by_name(np, "cpu_1x"); + if (WARN_ON(IS_ERR(clk))) + return; + + err = clk_prepare_enable(clk); + if (WARN_ON(err)) + return; + + ttccs->xttc.base_addr = base + reg * 4; + + ttccs->cs.name = np->name; + ttccs->cs.rating = 200; + ttccs->cs.read = __xttc_clocksource_read; + ttccs->cs.mask = CLOCKSOURCE_MASK(16); + ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET); + __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, + ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(CNT_CNTRL_RESET, + ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + + err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE); + if (WARN_ON(err)) + return; +} + +static void __init zynq_ttc_setup_clockevent(struct device_node *np, + void __iomem *base) +{ + struct xttcpss_timer_clockevent *ttcce; + int err, irq; + u32 reg; + + ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); + if (WARN_ON(!ttcce)) + return; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + ttcce->xttc.base_addr = base + reg * 4; + + ttcce->clk = of_clk_get_by_name(np, "cpu_1x"); + if (WARN_ON(IS_ERR(ttcce->clk))) + return; + + err = clk_prepare_enable(ttcce->clk); + if (WARN_ON(err)) + return; + + irq = irq_of_parse_and_map(np, 0); + if (WARN_ON(!irq)) + return; + + ttcce->ce.name = np->name; + ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + ttcce->ce.set_next_event = xttcpss_set_next_event; + ttcce->ce.set_mode = xttcpss_set_mode; + ttcce->ce.rating = 200; + ttcce->ce.irq = irq; + + __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, + ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET); + + err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER, + np->name, ttcce); + if (WARN_ON(err)) + return; + + clockevents_config_and_register(&ttcce->ce, + clk_get_rate(ttcce->clk) / PRESCALE, + 1, 0xfffe); +} + +static const __initconst struct of_device_id zynq_ttc_match[] = { + { .compatible = "xlnx,ttc-counter-clocksource", + .data = zynq_ttc_setup_clocksource, }, + { .compatible = "xlnx,ttc-counter-clockevent", + .data = zynq_ttc_setup_clockevent, }, + {} }; /** @@ -270,21 +309,25 @@ static struct clock_event_device xttcpss_clockevent = { **/ void __init xttcpss_timer_init(void) { - xttcpss_timer_hardware_init(); - clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); + struct device_node *np; - /* Calculate the parameters to allow the clockevent to operate using - integer math - */ - clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4); + for_each_compatible_node(np, NULL, "xlnx,ttc") { + struct device_node *np_chld; + void __iomem *base; - xttcpss_clockevent.max_delta_ns = - clockevent_delta2ns(0xfffe, &xttcpss_clockevent); - xttcpss_clockevent.min_delta_ns = - clockevent_delta2ns(1, &xttcpss_clockevent); + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; - /* Indicate that clock event is on 1st CPU as SMP boot needs it */ + for_each_available_child_of_node(np, np_chld) { + int (*cb)(struct device_node *np, void __iomem *base); + const struct of_device_id *match; - xttcpss_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&xttcpss_clockevent); + match = of_match_node(zynq_ttc_match, np_chld); + if (match) { + cb = match->data; + cb(np_chld, base); + } + } + } }