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NTB: move ntb_ctrl handling to init and deinit

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It does not really make sense to enable or disable
the bits of NTB_CTRL register only during enable
and disable link callbacks. They should be done
independent of these callbacks. The correct placement
for that is during the amd_init_side_info() and
amd_deinit_side_info() functions, which are invoked
during probe and remove respectively.

Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
This commit is contained in:
Arindam Nath 2020-02-05 21:24:27 +05:30 committed by Jon Mason
parent 673dd0c247
commit 92abf4cb99
1 changed files with 10 additions and 10 deletions
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20
drivers/ntb/hw/amd/ntb_hw_amd.c
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@ -290,7 +290,6 @@ static int amd_ntb_link_enable(struct ntb_dev *ntb,
{ {
struct amd_ntb_dev *ndev = ntb_ndev(ntb); struct amd_ntb_dev *ndev = ntb_ndev(ntb);
void __iomem *mmio = ndev->self_mmio; void __iomem *mmio = ndev->self_mmio;
u32 ntb_ctl;
/* Enable event interrupt */ /* Enable event interrupt */
ndev->int_mask &= ~AMD_EVENT_INTMASK; ndev->int_mask &= ~AMD_EVENT_INTMASK;
@ -300,10 +299,6 @@ static int amd_ntb_link_enable(struct ntb_dev *ntb,
return -EINVAL; return -EINVAL;
dev_dbg(&ntb->pdev->dev, "Enabling Link.\n"); dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
ntb_ctl |= (PMM_REG_CTL | SMM_REG_CTL);
writel(ntb_ctl, mmio + AMD_CNTL_OFFSET);
return 0; return 0;
} }
@ -311,7 +306,6 @@ static int amd_ntb_link_disable(struct ntb_dev *ntb)
{ {
struct amd_ntb_dev *ndev = ntb_ndev(ntb); struct amd_ntb_dev *ndev = ntb_ndev(ntb);
void __iomem *mmio = ndev->self_mmio; void __iomem *mmio = ndev->self_mmio;
u32 ntb_ctl;
/* Disable event interrupt */ /* Disable event interrupt */
ndev->int_mask |= AMD_EVENT_INTMASK; ndev->int_mask |= AMD_EVENT_INTMASK;
@ -321,10 +315,6 @@ static int amd_ntb_link_disable(struct ntb_dev *ntb)
return -EINVAL; return -EINVAL;
dev_dbg(&ntb->pdev->dev, "Enabling Link.\n"); dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
ntb_ctl &= ~(PMM_REG_CTL | SMM_REG_CTL);
writel(ntb_ctl, mmio + AMD_CNTL_OFFSET);
return 0; return 0;
} }
@ -927,18 +917,24 @@ static void amd_init_side_info(struct amd_ntb_dev *ndev)
{ {
void __iomem *mmio = ndev->self_mmio; void __iomem *mmio = ndev->self_mmio;
unsigned int reg; unsigned int reg;
u32 ntb_ctl;
reg = readl(mmio + AMD_SIDEINFO_OFFSET); reg = readl(mmio + AMD_SIDEINFO_OFFSET);
if (!(reg & AMD_SIDE_READY)) { if (!(reg & AMD_SIDE_READY)) {
reg |= AMD_SIDE_READY; reg |= AMD_SIDE_READY;
writel(reg, mmio + AMD_SIDEINFO_OFFSET); writel(reg, mmio + AMD_SIDEINFO_OFFSET);
} }
ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
ntb_ctl |= (PMM_REG_CTL | SMM_REG_CTL);
writel(ntb_ctl, mmio + AMD_CNTL_OFFSET);
} }
static void amd_deinit_side_info(struct amd_ntb_dev *ndev) static void amd_deinit_side_info(struct amd_ntb_dev *ndev)
{ {
void __iomem *mmio = ndev->self_mmio; void __iomem *mmio = ndev->self_mmio;
unsigned int reg; unsigned int reg;
u32 ntb_ctl;
reg = readl(mmio + AMD_SIDEINFO_OFFSET); reg = readl(mmio + AMD_SIDEINFO_OFFSET);
if (reg & AMD_SIDE_READY) { if (reg & AMD_SIDE_READY) {
@ -946,6 +942,10 @@ static void amd_deinit_side_info(struct amd_ntb_dev *ndev)
writel(reg, mmio + AMD_SIDEINFO_OFFSET); writel(reg, mmio + AMD_SIDEINFO_OFFSET);
readl(mmio + AMD_SIDEINFO_OFFSET); readl(mmio + AMD_SIDEINFO_OFFSET);
} }
ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
ntb_ctl &= ~(PMM_REG_CTL | SMM_REG_CTL);
writel(ntb_ctl, mmio + AMD_CNTL_OFFSET);
} }
static int amd_init_ntb(struct amd_ntb_dev *ndev) static int amd_init_ntb(struct amd_ntb_dev *ndev)