forked from luck/tmp_suning_uos_patched
mfd: asic3: Make use of raw_spinlock variants
The asic3 mfd driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Julia Cartwright
Lee Jones
parent
0c227c51b9
commit
93ad447191
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@ -78,7 +78,7 @@ struct asic3 {
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unsigned int bus_shift;
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unsigned int irq_nr;
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unsigned int irq_base;
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spinlock_t lock;
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raw_spinlock_t lock;
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u16 irq_bothedge[4];
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struct gpio_chip gpio;
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struct device *dev;
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@ -108,14 +108,14 @@ static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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val = asic3_read_register(asic, reg);
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if (set)
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val |= bits;
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else
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val &= ~bits;
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asic3_write_register(asic, reg, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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/* IRQs */
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@ -129,13 +129,13 @@ static void asic3_irq_flip_edge(struct asic3 *asic,
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u16 edge;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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edge = asic3_read_register(asic,
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base + ASIC3_GPIO_EDGE_TRIGGER);
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edge ^= bit;
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asic3_write_register(asic,
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base + ASIC3_GPIO_EDGE_TRIGGER, edge);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_irq_demux(struct irq_desc *desc)
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@ -151,10 +151,10 @@ static void asic3_irq_demux(struct irq_desc *desc)
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u32 status;
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int bank;
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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status = asic3_read_register(asic,
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ASIC3_OFFSET(INTR, P_INT_STAT));
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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/* Check all ten register bits */
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if ((status & 0x3ff) == 0)
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@ -167,7 +167,7 @@ static void asic3_irq_demux(struct irq_desc *desc)
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base = ASIC3_GPIO_A_BASE
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+ bank * ASIC3_GPIO_BASE_INCR;
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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istat = asic3_read_register(asic,
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base +
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ASIC3_GPIO_INT_STATUS);
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@ -175,7 +175,7 @@ static void asic3_irq_demux(struct irq_desc *desc)
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asic3_write_register(asic,
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base +
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ASIC3_GPIO_INT_STATUS, 0);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
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int bit = (1 << i);
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@ -230,11 +230,11 @@ static void asic3_mask_gpio_irq(struct irq_data *data)
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bank = asic3_irq_to_bank(asic, data->irq);
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index = asic3_irq_to_index(asic, data->irq);
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
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val |= 1 << index;
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asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_mask_irq(struct irq_data *data)
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@ -243,7 +243,7 @@ static void asic3_mask_irq(struct irq_data *data)
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int regval;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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regval = asic3_read_register(asic,
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ASIC3_INTR_BASE +
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ASIC3_INTR_INT_MASK);
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@ -255,7 +255,7 @@ static void asic3_mask_irq(struct irq_data *data)
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ASIC3_INTR_BASE +
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ASIC3_INTR_INT_MASK,
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regval);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_unmask_gpio_irq(struct irq_data *data)
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@ -267,11 +267,11 @@ static void asic3_unmask_gpio_irq(struct irq_data *data)
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bank = asic3_irq_to_bank(asic, data->irq);
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index = asic3_irq_to_index(asic, data->irq);
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
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val &= ~(1 << index);
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asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_unmask_irq(struct irq_data *data)
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@ -280,7 +280,7 @@ static void asic3_unmask_irq(struct irq_data *data)
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int regval;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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regval = asic3_read_register(asic,
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ASIC3_INTR_BASE +
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ASIC3_INTR_INT_MASK);
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@ -292,7 +292,7 @@ static void asic3_unmask_irq(struct irq_data *data)
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ASIC3_INTR_BASE +
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ASIC3_INTR_INT_MASK,
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regval);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
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@ -306,7 +306,7 @@ static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
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index = asic3_irq_to_index(asic, data->irq);
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bit = 1<<index;
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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level = asic3_read_register(asic,
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bank + ASIC3_GPIO_LEVEL_TRIGGER);
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edge = asic3_read_register(asic,
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@ -348,7 +348,7 @@ static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
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edge);
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asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
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trigger);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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return 0;
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}
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@ -455,7 +455,7 @@ static int asic3_gpio_direction(struct gpio_chip *chip,
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return -EINVAL;
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}
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
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@ -467,7 +467,7 @@ static int asic3_gpio_direction(struct gpio_chip *chip,
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asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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return 0;
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@ -524,7 +524,7 @@ static void asic3_gpio_set(struct gpio_chip *chip,
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mask = ASIC3_GPIO_TO_MASK(offset);
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
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@ -535,7 +535,7 @@ static void asic3_gpio_set(struct gpio_chip *chip,
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asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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@ -611,13 +611,13 @@ static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
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unsigned long flags;
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u32 cdex;
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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if (clk->enabled++ == 0) {
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cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
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cdex |= clk->cdex;
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asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
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}
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
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@ -627,13 +627,13 @@ static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
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WARN_ON(clk->enabled == 0);
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spin_lock_irqsave(&asic->lock, flags);
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raw_spin_lock_irqsave(&asic->lock, flags);
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if (--clk->enabled == 0) {
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cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
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cdex &= ~clk->cdex;
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asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
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}
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spin_unlock_irqrestore(&asic->lock, flags);
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raw_spin_unlock_irqrestore(&asic->lock, flags);
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}
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/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
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@ -963,7 +963,7 @@ static int __init asic3_probe(struct platform_device *pdev)
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if (!asic)
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return -ENOMEM;
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spin_lock_init(&asic->lock);
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raw_spin_lock_init(&asic->lock);
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platform_set_drvdata(pdev, asic);
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asic->dev = &pdev->dev;
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