forked from luck/tmp_suning_uos_patched
dma : EG20T PCH: Fix miss-setting DMA descriptor
Currently, in case of using scatter/gather mode, head of data is not sent to destination. The cause is second descriptor address is set to NEXT. The NEXT must have head of descriptor address. This patch sets head of descriptor address to the NEXT. Acked-by: Yong Wang <youg.y.wang@intel.com> Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> [dan.j.williams@intel.com: fixed up usage of virt_to_phys()] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -259,11 +259,6 @@ static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc)
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return;
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}
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channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
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channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
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channel_writel(pd_chan, SIZE, desc->regs.size);
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channel_writel(pd_chan, NEXT, desc->regs.next);
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dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n",
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pd_chan->chan.chan_id, desc->regs.dev_addr);
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dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n",
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@ -273,10 +268,16 @@ static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc)
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dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n",
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pd_chan->chan.chan_id, desc->regs.next);
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if (list_empty(&desc->tx_list))
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if (list_empty(&desc->tx_list)) {
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channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
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channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
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channel_writel(pd_chan, SIZE, desc->regs.size);
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channel_writel(pd_chan, NEXT, desc->regs.next);
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pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT);
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else
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} else {
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channel_writel(pd_chan, NEXT, desc->txd.phys);
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pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG);
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}
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val = dma_readl(pd, CTL2);
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val |= 1 << (DMA_CTL2_START_SHIFT_BITS + pd_chan->chan.chan_id);
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