AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

drm/radeon: 9800 SE has only one quadpipe

Browse Source 
Although these cards have 2 pipelines on the silicon only
the first passed the QA and the other should be disabled.

http://www.digital-daily.com/video/ati-radeon9800se/
http://www.rojakpot.com/showarticle.aspx?artno=101&pgno=1

agd5f: add some other SE cards as well; fix up kms

Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Tormod Volden 2010-04-22 16:57:32 -04:00 committed by Dave Airlie
parent 9c950a43dd
commit 94f7bf6473
3 changed files with 15 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/radeon/r300.c
View File

@ -323,13 +323,12 @@ void r300_gpu_init(struct radeon_device *rdev)
uint32_t gb_tile_config, tmp; uint32_t gb_tile_config, tmp;
r100_hdp_reset(rdev); r100_hdp_reset(rdev);
/* FIXME: rv380 one pipes ? */
if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
(rdev->family == CHIP_R350)) { (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
/* r300,r350 */ /* r300,r350 */
rdev->num_gb_pipes = 2; rdev->num_gb_pipes = 2;
} else { } else {
/* rv350,rv370,rv380,r300 AD */ /* rv350,rv370,rv380,r300 AD, r350 AH */
rdev->num_gb_pipes = 1; rdev->num_gb_pipes = 1;
} }
rdev->num_z_pipes = 1; rdev->num_z_pipes = 1;

6
drivers/gpu/drm/radeon/r420.c
View File

@ -58,6 +58,12 @@ void r420_pipes_init(struct radeon_device *rdev)
/* get max number of pipes */ /* get max number of pipes */
gb_pipe_select = RREG32(0x402C); gb_pipe_select = RREG32(0x402C);
num_pipes = ((gb_pipe_select >> 12) & 3) + 1; num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
/* SE chips have 1 pipe */
if ((rdev->pdev->device == 0x5e4c) ||
(rdev->pdev->device == 0x5e4f))
num_pipes = 1;
rdev->num_gb_pipes = num_pipes; rdev->num_gb_pipes = num_pipes;
tmp = 0; tmp = 0;
switch (num_pipes) { switch (num_pipes) {

9
drivers/gpu/drm/radeon/radeon_cp.c
View File

@ -435,14 +435,19 @@ static void radeon_init_pipes(struct drm_device *dev)
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
/* SE cards have 1 pipe */
if ((dev->pdev->device == 0x5e4c) ||
(dev->pdev->device == 0x5e4f))
dev_priv->num_gb_pipes = 1;
} else { } else {
/* R3xx */ /* R3xx */
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 && if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
dev->pdev->device != 0x4144) || dev->pdev->device != 0x4144) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
dev->pdev->device != 0x4148)) {
dev_priv->num_gb_pipes = 2; dev_priv->num_gb_pipes = 2;
} else { } else {
/* RV3xx/R300 AD */ /* RV3xx/R300 AD/R350 AH */
dev_priv->num_gb_pipes = 1; dev_priv->num_gb_pipes = 1;
} }
} }