forked from luck/tmp_suning_uos_patched
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT
Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
This commit is contained in:
Shawn Lin
Lorenzo Pieralisi
parent
956cd99b35
commit
964bac9455
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@ -705,130 +705,20 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
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}
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/**
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* rockchip_pcie_parse_dt - Parse Device Tree
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* rockchip_pcie_parse_host_dt - Parse Device Tree
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* @rockchip: PCIe port information
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*
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* Return: '0' on success and error value on failure
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*/
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static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
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static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct device_node *node = dev->of_node;
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struct resource *regs;
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int err;
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regs = platform_get_resource_byname(pdev,
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IORESOURCE_MEM,
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"axi-base");
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rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(rockchip->reg_base))
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return PTR_ERR(rockchip->reg_base);
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regs = platform_get_resource_byname(pdev,
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IORESOURCE_MEM,
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"apb-base");
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rockchip->apb_base = devm_ioremap_resource(dev, regs);
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if (IS_ERR(rockchip->apb_base))
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return PTR_ERR(rockchip->apb_base);
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err = rockchip_pcie_get_phys(rockchip);
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err = rockchip_pcie_parse_dt(rockchip);
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if (err)
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return err;
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rockchip->lanes = 1;
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err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
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if (!err && (rockchip->lanes == 0 ||
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rockchip->lanes == 3 ||
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rockchip->lanes > 4)) {
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dev_warn(dev, "invalid num-lanes, default to use one lane\n");
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rockchip->lanes = 1;
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}
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rockchip->link_gen = of_pci_get_max_link_speed(node);
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if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
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rockchip->link_gen = 2;
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rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
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if (IS_ERR(rockchip->core_rst)) {
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if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing core reset property in node\n");
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return PTR_ERR(rockchip->core_rst);
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}
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rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
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if (IS_ERR(rockchip->mgmt_rst)) {
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if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing mgmt reset property in node\n");
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return PTR_ERR(rockchip->mgmt_rst);
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}
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rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
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"mgmt-sticky");
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if (IS_ERR(rockchip->mgmt_sticky_rst)) {
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if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing mgmt-sticky reset property in node\n");
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return PTR_ERR(rockchip->mgmt_sticky_rst);
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}
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rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
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if (IS_ERR(rockchip->pipe_rst)) {
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if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pipe reset property in node\n");
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return PTR_ERR(rockchip->pipe_rst);
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}
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rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
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if (IS_ERR(rockchip->pm_rst)) {
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if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pm reset property in node\n");
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return PTR_ERR(rockchip->pm_rst);
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}
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rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
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if (IS_ERR(rockchip->pclk_rst)) {
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if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pclk reset property in node\n");
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return PTR_ERR(rockchip->pclk_rst);
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}
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rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
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if (IS_ERR(rockchip->aclk_rst)) {
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if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing aclk reset property in node\n");
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return PTR_ERR(rockchip->aclk_rst);
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}
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rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
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if (IS_ERR(rockchip->ep_gpio)) {
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dev_err(dev, "missing ep-gpios property in node\n");
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return PTR_ERR(rockchip->ep_gpio);
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}
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rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
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if (IS_ERR(rockchip->aclk_pcie)) {
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dev_err(dev, "aclk clock not found\n");
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return PTR_ERR(rockchip->aclk_pcie);
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}
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rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
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if (IS_ERR(rockchip->aclk_perf_pcie)) {
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dev_err(dev, "aclk_perf clock not found\n");
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return PTR_ERR(rockchip->aclk_perf_pcie);
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}
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rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
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if (IS_ERR(rockchip->hclk_pcie)) {
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dev_err(dev, "hclk clock not found\n");
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return PTR_ERR(rockchip->hclk_pcie);
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}
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rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
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if (IS_ERR(rockchip->clk_pcie_pm)) {
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dev_err(dev, "pm clock not found\n");
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return PTR_ERR(rockchip->clk_pcie_pm);
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}
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err = rockchip_pcie_setup_irq(rockchip);
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if (err)
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return err;
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@ -1195,8 +1085,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, rockchip);
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rockchip->dev = dev;
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rockchip->is_rc = true;
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err = rockchip_pcie_parse_dt(rockchip);
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err = rockchip_pcie_parse_host_dt(rockchip);
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if (err)
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return err;
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@ -12,10 +12,139 @@
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*/
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/of_pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "pcie-rockchip.h"
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int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct device_node *node = dev->of_node;
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struct resource *regs;
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int err;
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regs = platform_get_resource_byname(pdev,
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IORESOURCE_MEM,
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"axi-base");
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rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(rockchip->reg_base))
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return PTR_ERR(rockchip->reg_base);
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regs = platform_get_resource_byname(pdev,
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IORESOURCE_MEM,
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"apb-base");
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rockchip->apb_base = devm_ioremap_resource(dev, regs);
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if (IS_ERR(rockchip->apb_base))
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return PTR_ERR(rockchip->apb_base);
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err = rockchip_pcie_get_phys(rockchip);
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if (err)
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return err;
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rockchip->lanes = 1;
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err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
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if (!err && (rockchip->lanes == 0 ||
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rockchip->lanes == 3 ||
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rockchip->lanes > 4)) {
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dev_warn(dev, "invalid num-lanes, default to use one lane\n");
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rockchip->lanes = 1;
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}
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rockchip->link_gen = of_pci_get_max_link_speed(node);
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if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
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rockchip->link_gen = 2;
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rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
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if (IS_ERR(rockchip->core_rst)) {
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if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing core reset property in node\n");
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return PTR_ERR(rockchip->core_rst);
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}
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rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
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if (IS_ERR(rockchip->mgmt_rst)) {
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if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing mgmt reset property in node\n");
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return PTR_ERR(rockchip->mgmt_rst);
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}
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rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
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"mgmt-sticky");
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if (IS_ERR(rockchip->mgmt_sticky_rst)) {
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if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing mgmt-sticky reset property in node\n");
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return PTR_ERR(rockchip->mgmt_sticky_rst);
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}
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rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
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if (IS_ERR(rockchip->pipe_rst)) {
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if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pipe reset property in node\n");
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return PTR_ERR(rockchip->pipe_rst);
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}
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rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
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if (IS_ERR(rockchip->pm_rst)) {
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if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pm reset property in node\n");
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return PTR_ERR(rockchip->pm_rst);
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}
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rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
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if (IS_ERR(rockchip->pclk_rst)) {
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if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing pclk reset property in node\n");
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return PTR_ERR(rockchip->pclk_rst);
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}
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rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
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if (IS_ERR(rockchip->aclk_rst)) {
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if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
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dev_err(dev, "missing aclk reset property in node\n");
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return PTR_ERR(rockchip->aclk_rst);
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}
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if (rockchip->is_rc) {
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rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
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if (IS_ERR(rockchip->ep_gpio)) {
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dev_err(dev, "missing ep-gpios property in node\n");
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return PTR_ERR(rockchip->ep_gpio);
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}
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}
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rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
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if (IS_ERR(rockchip->aclk_pcie)) {
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dev_err(dev, "aclk clock not found\n");
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return PTR_ERR(rockchip->aclk_pcie);
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}
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rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
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if (IS_ERR(rockchip->aclk_perf_pcie)) {
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dev_err(dev, "aclk_perf clock not found\n");
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return PTR_ERR(rockchip->aclk_perf_pcie);
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}
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rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
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if (IS_ERR(rockchip->hclk_pcie)) {
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dev_err(dev, "hclk clock not found\n");
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return PTR_ERR(rockchip->hclk_pcie);
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}
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rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
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if (IS_ERR(rockchip->clk_pcie_pm)) {
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dev_err(dev, "pm clock not found\n");
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return PTR_ERR(rockchip->clk_pcie_pm);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
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int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->dev;
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@ -222,6 +222,7 @@ struct rockchip_pcie {
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u32 mem_size;
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phys_addr_t msg_bus_addr;
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phys_addr_t mem_bus_addr;
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bool is_rc;
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};
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static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
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@ -235,6 +236,7 @@ static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
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writel(val, rockchip->apb_base + reg);
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}
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int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip);
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int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
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void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
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int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);
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