forked from luck/tmp_suning_uos_patched
iommu/amd: Fix sparse warnings
A few sparse warnings fire in drivers/iommu/amd_iommu_init.c. Fix most of them with this patch. Also fix the sparse warnings in drivers/iommu/irq_remapping.c while at it. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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@ -2073,7 +2073,7 @@ static int pdev_iommuv2_enable(struct pci_dev *pdev)
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/* FIXME: Move this to PCI code */
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#define PCI_PRI_TLP_OFF (1 << 15)
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bool pci_pri_tlp_required(struct pci_dev *pdev)
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static bool pci_pri_tlp_required(struct pci_dev *pdev)
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{
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u16 status;
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int pos;
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@ -190,12 +190,6 @@ static u32 dev_table_size; /* size of the device table */
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static u32 alias_table_size; /* size of the alias table */
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static u32 rlookup_table_size; /* size if the rlookup table */
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/*
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* This function flushes all internal caches of
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* the IOMMU used by this driver.
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*/
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extern void iommu_flush_all_caches(struct amd_iommu *iommu);
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static int amd_iommu_enable_interrupts(void);
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static inline void update_last_devid(u16 devid)
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@ -358,7 +352,7 @@ static void iommu_disable(struct amd_iommu *iommu)
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* mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
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* the system has one.
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*/
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static u8 * __init iommu_map_mmio_space(u64 address)
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static u8 __iomem * __init iommu_map_mmio_space(u64 address)
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{
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if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
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pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
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@ -367,7 +361,7 @@ static u8 * __init iommu_map_mmio_space(u64 address)
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return NULL;
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}
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return ioremap_nocache(address, MMIO_REGION_LENGTH);
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return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH);
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}
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static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
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@ -1217,7 +1211,7 @@ static int __init init_exclusion_range(struct ivmd_header *m)
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/* called for unity map ACPI definition */
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static int __init init_unity_map_range(struct ivmd_header *m)
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{
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struct unity_map_entry *e = 0;
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struct unity_map_entry *e = NULL;
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char *s;
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e = kzalloc(sizeof(*e), GFP_KERNEL);
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@ -1727,8 +1721,8 @@ __setup("amd_iommu=", parse_amd_iommu_options);
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IOMMU_INIT_FINISH(amd_iommu_detect,
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gart_iommu_hole_init,
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0,
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0);
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NULL,
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NULL);
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bool amd_iommu_v2_supported(void)
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{
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@ -487,7 +487,7 @@ struct amd_iommu {
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/* physical address of MMIO space */
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u64 mmio_phys;
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/* virtual address of MMIO space */
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u8 *mmio_base;
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u8 __iomem *mmio_base;
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/* capabilities of that IOMMU read from ACPI */
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u32 cap;
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@ -664,6 +664,12 @@ extern bool amd_iommu_force_isolation;
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/* Max levels of glxval supported */
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extern int amd_iommu_max_glx_val;
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/*
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* This function flushes all internal caches of
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* the IOMMU used by this driver.
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*/
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extern void iommu_flush_all_caches(struct amd_iommu *iommu);
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/* takes bus and device/function and returns the device id
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* FIXME: should that be in generic PCI code? */
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static inline u16 calc_devid(u8 bus, u8 devfn)
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@ -81,7 +81,7 @@ struct fault {
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u16 flags;
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};
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struct device_state **state_table;
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static struct device_state **state_table;
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static spinlock_t state_lock;
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/* List and lock for all pasid_states */
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@ -1,6 +1,11 @@
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/cpumask.h>
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#include <linux/errno.h>
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#include <linux/msi.h>
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#include <asm/hw_irq.h>
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#include <asm/irq_remapping.h>
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#include "irq_remapping.h"
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