forked from luck/tmp_suning_uos_patched
cirrusfb: eliminate CRT registers from global structure
Move calculations of CRT register values into the cirrusfb_set_par_foo() where the values are used. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Krzysztof Helt
Linus Torvalds
parent
c395d3e8c7
commit
9a85cf51fb
@ -334,22 +334,6 @@ struct cirrusfb_regs {
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long multiplexing;
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long mclk;
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long divMCLK;
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long HorizRes; /* The x resolution in pixel */
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long HorizTotal;
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long HorizDispEnd;
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long HorizBlankStart;
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long HorizBlankEnd;
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long HorizSyncStart;
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long HorizSyncEnd;
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long VertRes; /* the physical y resolution in scanlines */
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long VertTotal;
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long VertDispEnd;
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long VertSyncStart;
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long VertSyncEnd;
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long VertBlankStart;
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long VertBlankEnd;
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};
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#ifdef CIRRUSFB_DEBUG
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@ -664,8 +648,6 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
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long maxclock;
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int maxclockidx = var->bits_per_pixel >> 3;
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struct cirrusfb_info *cinfo = info->par;
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int xres, hfront, hsync, hback;
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int yres, vfront, vsync, vback;
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switch (var->bits_per_pixel) {
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case 1:
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@ -723,7 +705,7 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
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switch (var->bits_per_pixel) {
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case 16:
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case 32:
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if (regs->HorizRes <= 800)
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if (var->xres <= 800)
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/* Xbh has this type of clock for 32-bit */
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freq /= 2;
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break;
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@ -735,57 +717,6 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
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regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
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®s->divMCLK);
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xres = var->xres;
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hfront = var->right_margin;
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hsync = var->hsync_len;
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hback = var->left_margin;
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yres = var->yres;
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vfront = var->lower_margin;
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vsync = var->vsync_len;
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vback = var->upper_margin;
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if (var->vmode & FB_VMODE_DOUBLE) {
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yres *= 2;
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vfront *= 2;
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vsync *= 2;
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vback *= 2;
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} else if (var->vmode & FB_VMODE_INTERLACED) {
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yres = (yres + 1) / 2;
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vfront = (vfront + 1) / 2;
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vsync = (vsync + 1) / 2;
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vback = (vback + 1) / 2;
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}
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regs->HorizRes = xres;
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regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
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regs->HorizDispEnd = xres / 8 - 1;
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regs->HorizBlankStart = xres / 8;
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/* does not count with "-5" */
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regs->HorizBlankEnd = regs->HorizTotal + 5;
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regs->HorizSyncStart = (xres + hfront) / 8 + 1;
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regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
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regs->VertRes = yres;
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regs->VertTotal = yres + vfront + vsync + vback - 2;
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regs->VertDispEnd = yres - 1;
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regs->VertBlankStart = yres;
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regs->VertBlankEnd = regs->VertTotal;
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regs->VertSyncStart = yres + vfront - 1;
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regs->VertSyncEnd = yres + vfront + vsync - 1;
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if (regs->VertRes >= 1024) {
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regs->VertTotal /= 2;
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regs->VertSyncStart /= 2;
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regs->VertSyncEnd /= 2;
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regs->VertDispEnd /= 2;
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}
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if (regs->multiplexing) {
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regs->HorizTotal /= 2;
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regs->HorizSyncStart /= 2;
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regs->HorizSyncEnd /= 2;
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regs->HorizDispEnd /= 2;
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}
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return 0;
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}
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@ -823,6 +754,8 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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unsigned char tmp;
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int offset = 0, err;
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const struct cirrusfb_board_info_rec *bi;
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int hdispend, hsyncstart, hsyncend, htotal;
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int yres, vdispend, vsyncstart, vsyncend, vtotal;
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DPRINTK("ENTER\n");
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DPRINTK("Requested mode: %dx%dx%d\n",
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@ -840,76 +773,117 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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bi = &cirrusfb_board_info[cinfo->btype];
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hsyncstart = var->xres + var->right_margin;
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hsyncend = hsyncstart + var->hsync_len;
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htotal = (hsyncend + var->left_margin) / 8 - 5;
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hdispend = var->xres / 8 - 1;
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hsyncstart = hsyncstart / 8 + 1;
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hsyncend = hsyncend / 8 + 1;
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yres = var->yres;
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vsyncstart = yres + var->lower_margin;
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vsyncend = vsyncstart + var->vsync_len;
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vtotal = vsyncend + var->upper_margin;
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vdispend = yres - 1;
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if (var->vmode & FB_VMODE_DOUBLE) {
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yres *= 2;
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vsyncstart *= 2;
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vsyncend *= 2;
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vtotal *= 2;
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} else if (var->vmode & FB_VMODE_INTERLACED) {
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yres = (yres + 1) / 2;
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vsyncstart = (vsyncstart + 1) / 2;
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vsyncend = (vsyncend + 1) / 2;
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vtotal = (vtotal + 1) / 2;
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}
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vtotal -= 2;
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vsyncstart -= 1;
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vsyncend -= 1;
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if (yres >= 1024) {
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vtotal /= 2;
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vsyncstart /= 2;
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vsyncend /= 2;
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vdispend /= 2;
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}
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if (regs.multiplexing) {
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htotal /= 2;
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hsyncstart /= 2;
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hsyncend /= 2;
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hdispend /= 2;
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}
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/* unlock register VGA_CRTC_H_TOTAL..CRT7 */
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vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
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/* if debugging is enabled, all parameters get output before writing */
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DPRINTK("CRT0: %ld\n", regs.HorizTotal);
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vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
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DPRINTK("CRT0: %d\n", htotal);
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vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
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DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
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vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
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DPRINTK("CRT1: %d\n", hdispend);
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vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
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DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
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vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
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DPRINTK("CRT2: %d\n", var->xres / 8);
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vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
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/* + 128: Compatible read */
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DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
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DPRINTK("CRT3: 128+%d\n", (htotal + 5) % 32);
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vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
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128 + (regs.HorizBlankEnd % 32));
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128 + ((htotal + 5) % 32));
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DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
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vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
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DPRINTK("CRT4: %d\n", hsyncstart);
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vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
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tmp = regs.HorizSyncEnd % 32;
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if (regs.HorizBlankEnd & 32)
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tmp = hsyncend % 32;
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if ((htotal + 5) & 32)
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tmp += 128;
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DPRINTK("CRT5: %d\n", tmp);
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vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
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DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
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DPRINTK("CRT6: %d\n", vtotal & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
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tmp = 16; /* LineCompare bit #9 */
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if (regs.VertTotal & 256)
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if (vtotal & 256)
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tmp |= 1;
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if (regs.VertDispEnd & 256)
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if (vdispend & 256)
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tmp |= 2;
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if (regs.VertSyncStart & 256)
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if (vsyncstart & 256)
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tmp |= 4;
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if (regs.VertBlankStart & 256)
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if ((vdispend + 1) & 256)
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tmp |= 8;
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if (regs.VertTotal & 512)
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if (vtotal & 512)
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tmp |= 32;
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if (regs.VertDispEnd & 512)
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if (vdispend & 512)
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tmp |= 64;
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if (regs.VertSyncStart & 512)
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if (vsyncstart & 512)
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tmp |= 128;
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DPRINTK("CRT7: %d\n", tmp);
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vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
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tmp = 0x40; /* LineCompare bit #8 */
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if (regs.VertBlankStart & 512)
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if ((vdispend + 1) & 512)
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tmp |= 0x20;
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if (var->vmode & FB_VMODE_DOUBLE)
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tmp |= 0x80;
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DPRINTK("CRT9: %d\n", tmp);
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vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
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DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart & 0xff);
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DPRINTK("CRT10: %d\n", vsyncstart & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
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DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
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vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd % 16 + 64 + 32);
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DPRINTK("CRT11: 64+32+%d\n", vsyncend % 16);
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vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
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DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd & 0xff);
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DPRINTK("CRT12: %d\n", vdispend & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
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DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.VertBlankStart & 0xff);
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DPRINTK("CRT15: %d\n", (vdispend + 1) & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
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DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd & 0xff);
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DPRINTK("CRT16: %d\n", vtotal & 0xff);
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vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
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DPRINTK("CRT18: 0xff\n");
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vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
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@ -917,13 +891,13 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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tmp = 0;
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if (var->vmode & FB_VMODE_INTERLACED)
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tmp |= 1;
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if (regs.HorizBlankEnd & 64)
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if ((htotal + 5) & 64)
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tmp |= 16;
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if (regs.HorizBlankEnd & 128)
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if ((htotal + 5) & 128)
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tmp |= 32;
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if (regs.VertBlankEnd & 256)
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if (vtotal & 256)
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tmp |= 64;
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if (regs.VertBlankEnd & 512)
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if (vtotal & 512)
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tmp |= 128;
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DPRINTK("CRT1a: %d\n", tmp);
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@ -948,7 +922,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
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vga_wseq(regbase, CL_SEQR1B, tmp);
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if (regs.VertRes >= 1024)
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if (yres >= 1024)
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/* 1280x1024 */
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vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
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else
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@ -962,7 +936,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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/* don't know if it would hurt to also program this if no interlaced */
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/* mode is used, but I feel better this way.. :-) */
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if (var->vmode & FB_VMODE_INTERLACED)
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vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
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vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
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else
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vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
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@ -1208,7 +1182,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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case BT_ALPINE:
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DPRINTK(" (for GD543x)\n");
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if (regs.HorizRes >= 1024)
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if (var->xres >= 1024)
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vga_wseq(regbase, CL_SEQR7, 0xa7);
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else
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vga_wseq(regbase, CL_SEQR7, 0xa3);
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