forked from luck/tmp_suning_uos_patched
clk: mediatek: Remove ifr{0,1}_cfg_regs structures
These aren't used and the macros that reference them aren't used either.
Remove the dead code to avoid compile warnings.
Cc: Owen Chen <owen.chen@mediatek.com>
Cc: Mars Cheng <mars.cheng@mediatek.com>
Cc: Macpaul Lin <macpaul.lin@mediatek.com>
Fixes: 1aca9939bf
("clk: mediatek: Add MT6765 clock support")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200609211847.27366-1-sboyd@kernel.org
This commit is contained in:
parent
45edc7e274
commit
9ac1eafa88
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@ -534,18 +534,6 @@ static const struct mtk_gate top_clks[] = {
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GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
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};
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static const struct mtk_gate_regs ifr0_cg_regs = {
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.set_ofs = 0x200,
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.clr_ofs = 0x200,
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.sta_ofs = 0x200,
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};
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static const struct mtk_gate_regs ifr1_cg_regs = {
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.set_ofs = 0x74,
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.clr_ofs = 0x74,
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.sta_ofs = 0x74,
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};
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static const struct mtk_gate_regs ifr2_cg_regs = {
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.set_ofs = 0x80,
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.clr_ofs = 0x84,
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@ -570,24 +558,6 @@ static const struct mtk_gate_regs ifr5_cg_regs = {
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.sta_ofs = 0xc8,
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};
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#define GATE_IFR0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ifr0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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#define GATE_IFR1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ifr1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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#define GATE_IFR2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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