forked from luck/tmp_suning_uos_patched
KVM: x86/mmu: fix NULL pointer dereference on guest INVPCID
commit 9f46c187e2e680ecd9de7983e4d081c3391acc76 upstream. With shadow paging enabled, the INVPCID instruction results in a call to kvm_mmu_invpcid_gva. If INVPCID is executed with CR0.PG=0, the invlpg callback is not set and the result is a NULL pointer dereference. Fix it trivially by checking for mmu->invlpg before every call. There are other possibilities: - check for CR0.PG, because KVM (like all Intel processors after P5) flushes guest TLB on CR0.PG changes so that INVPCID/INVLPG are a nop with paging disabled - check for EFER.LMA, because KVM syncs and flushes when switching MMU contexts outside of 64-bit mode All of these are tricky, go for the simple solution. This is CVE-2022-1789. Reported-by: Yongkang Jia <kangel@zju.edu.cn> Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [fix conflict due to missing b9e5603c2a3accbadfec570ac501a54431a6bdba] Signed-off-by: Vegard Nossum <vegard.nossum@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -5178,14 +5178,16 @@ void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
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uint i;
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if (pcid == kvm_get_active_pcid(vcpu)) {
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mmu->invlpg(vcpu, gva, mmu->root_hpa);
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if (mmu->invlpg)
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mmu->invlpg(vcpu, gva, mmu->root_hpa);
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tlb_flush = true;
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}
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for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
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if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
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pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
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mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
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if (mmu->invlpg)
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mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
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tlb_flush = true;
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}
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}
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