ARM: S3C24XX: Add initial s3c_gpio configuration code

Add support for s3c_gpio_setcfg() and s3c_gpio_setpull() implementations
to get ready for removal of the specific code being used by s3c24xx.

Also rename the s3c_gpio_setcfg_s3c24xx_banka to s3c_gpio_setcfg_s3c24xx_a
as seen in the header file to correct a build warning.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks 2010-04-30 19:30:35 +09:00
parent 7ebd467551
commit 9bbb851c70
4 changed files with 22 additions and 3 deletions
arch/arm
plat-s3c24xx
plat-samsung

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@ -9,6 +9,7 @@ config PLAT_S3C24XX
select NO_IOPORT select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select S3C_DEVICE_NAND select S3C_DEVICE_NAND
select S3C_GPIO_CFG_S3C24XX
help help
Base platform code for any Samsung S3C24XX device Base platform code for any Samsung S3C24XX device

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@ -21,6 +21,8 @@
#include <linux/gpio.h> #include <linux/gpio.h>
#include <plat/gpio-core.h> #include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <plat/pm.h> #include <plat/pm.h>
@ -77,10 +79,19 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
return IRQ_EINT8 + offset; return IRQ_EINT8 + offset;
} }
static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
.set_config = s3c_gpio_setcfg_s3c24xx_a,
};
struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
.set_config = s3c_gpio_setcfg_s3c24xx,
};
struct s3c_gpio_chip s3c24xx_gpios[] = { struct s3c_gpio_chip s3c24xx_gpios[] = {
[0] = { [0] = {
.base = S3C2410_GPACON, .base = S3C2410_GPACON,
.pm = __gpio_pm(&s3c_gpio_pm_1bit), .pm = __gpio_pm(&s3c_gpio_pm_1bit),
.config = &s3c24xx_gpiocfg_banka,
.chip = { .chip = {
.base = S3C2410_GPA(0), .base = S3C2410_GPA(0),
.owner = THIS_MODULE, .owner = THIS_MODULE,
@ -168,8 +179,12 @@ static __init int s3c24xx_gpiolib_init(void)
struct s3c_gpio_chip *chip = s3c24xx_gpios; struct s3c_gpio_chip *chip = s3c24xx_gpios;
int gpn; int gpn;
for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
if (!chip->config)
chip->config = &s3c24xx_gpiocfg_default;
s3c_gpiolib_add(chip); s3c_gpiolib_add(chip);
}
return 0; return 0;
} }

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@ -61,8 +61,8 @@ int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
EXPORT_SYMBOL(s3c_gpio_setpull); EXPORT_SYMBOL(s3c_gpio_setpull);
#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg) unsigned int off, unsigned int cfg)
{ {
void __iomem *reg = chip->base; void __iomem *reg = chip->base;
unsigned int shift = off; unsigned int shift = off;

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@ -108,6 +108,9 @@ extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
/* exported for core SoC support to change */
extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
#ifdef CONFIG_S3C_GPIO_TRACK #ifdef CONFIG_S3C_GPIO_TRACK
extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];