forked from luck/tmp_suning_uos_patched
hwmon: Add hardware monitoring driver for Moortec MR75203 PVT controller
PVT controller (MR75203) is used to configure & control Moortec embedded analog IP which contains temprature sensor(TS), voltage monitor(VM) & process detector(PD) modules. Add hardware monitoring driver to support MR75203 PVT controller. Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/05b59cd860d2a1aa0a68ab300829efe709645184.1601889876.git.rahul.tanwar@linux.intel.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
This commit is contained in:
Rahul Tanwar
Guenter Roeck
parent
748022ef09
commit
9d823351a3
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@ -1112,6 +1112,16 @@ config SENSORS_MENF21BMC_HWMON
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This driver can also be built as a module. If so the module
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will be called menf21bmc_hwmon.
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config SENSORS_MR75203
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tristate "Moortec Semiconductor MR75203 PVT Controller"
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select REGMAP_MMIO
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help
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If you say yes here you get support for Moortec MR75203
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PVT controller.
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This driver can also be built as a module. If so, the module
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will be called mr75203.
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config SENSORS_ADCXX
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tristate "National Semiconductor ADCxxxSxxx"
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depends on SPI_MASTER
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@ -143,6 +143,7 @@ obj-$(CONFIG_SENSORS_MCP3021) += mcp3021.o
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obj-$(CONFIG_SENSORS_TC654) += tc654.o
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obj-$(CONFIG_SENSORS_MLXREG_FAN) += mlxreg-fan.o
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obj-$(CONFIG_SENSORS_MENF21BMC_HWMON) += menf21bmc_hwmon.o
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obj-$(CONFIG_SENSORS_MR75203) += mr75203.o
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obj-$(CONFIG_SENSORS_NCT6683) += nct6683.o
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obj-$(CONFIG_SENSORS_NCT6775) += nct6775.o
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obj-$(CONFIG_SENSORS_NCT7802) += nct7802.o
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656
drivers/hwmon/mr75203.c
Normal file
656
drivers/hwmon/mr75203.c
Normal file
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@ -0,0 +1,656 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MaxLinear, Inc.
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*
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* This driver is a hardware monitoring driver for PVT controller
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* (MR75203) which is used to configure & control Moortec embedded
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* analog IP to enable multiple embedded temperature sensor(TS),
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* voltage monitor(VM) & process detector(PD) modules.
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/hwmon.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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/* PVT Common register */
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#define PVT_IP_CONFIG 0x04
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#define TS_NUM_MSK GENMASK(4, 0)
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#define TS_NUM_SFT 0
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#define PD_NUM_MSK GENMASK(12, 8)
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#define PD_NUM_SFT 8
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#define VM_NUM_MSK GENMASK(20, 16)
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#define VM_NUM_SFT 16
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#define CH_NUM_MSK GENMASK(31, 24)
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#define CH_NUM_SFT 24
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/* Macro Common Register */
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#define CLK_SYNTH 0x00
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#define CLK_SYNTH_LO_SFT 0
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#define CLK_SYNTH_HI_SFT 8
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#define CLK_SYNTH_HOLD_SFT 16
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#define CLK_SYNTH_EN BIT(24)
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#define CLK_SYS_CYCLES_MAX 514
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#define CLK_SYS_CYCLES_MIN 2
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#define HZ_PER_MHZ 1000000L
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#define SDIF_DISABLE 0x04
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#define SDIF_STAT 0x08
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#define SDIF_BUSY BIT(0)
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#define SDIF_LOCK BIT(1)
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#define SDIF_W 0x0c
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#define SDIF_PROG BIT(31)
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#define SDIF_WRN_W BIT(27)
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#define SDIF_WRN_R 0x00
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#define SDIF_ADDR_SFT 24
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#define SDIF_HALT 0x10
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#define SDIF_CTRL 0x14
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#define SDIF_SMPL_CTRL 0x20
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/* TS & PD Individual Macro Register */
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#define COM_REG_SIZE 0x40
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#define SDIF_DONE(n) (COM_REG_SIZE + 0x14 + 0x40 * (n))
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#define SDIF_SMPL_DONE BIT(0)
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#define SDIF_DATA(n) (COM_REG_SIZE + 0x18 + 0x40 * (n))
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#define SAMPLE_DATA_MSK GENMASK(15, 0)
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#define HILO_RESET(n) (COM_REG_SIZE + 0x2c + 0x40 * (n))
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/* VM Individual Macro Register */
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#define VM_COM_REG_SIZE 0x200
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#define VM_SDIF_DONE(n) (VM_COM_REG_SIZE + 0x34 + 0x200 * (n))
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#define VM_SDIF_DATA(n) (VM_COM_REG_SIZE + 0x40 + 0x200 * (n))
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/* SDA Slave Register */
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#define IP_CTRL 0x00
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#define IP_RST_REL BIT(1)
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#define IP_RUN_CONT BIT(3)
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#define IP_AUTO BIT(8)
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#define IP_VM_MODE BIT(10)
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#define IP_CFG 0x01
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#define CFG0_MODE_2 BIT(0)
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#define CFG0_PARALLEL_OUT 0
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#define CFG0_12_BIT 0
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#define CFG1_VOL_MEAS_MODE 0
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#define CFG1_PARALLEL_OUT 0
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#define CFG1_14_BIT 0
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#define IP_DATA 0x03
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#define IP_POLL 0x04
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#define VM_CH_INIT BIT(20)
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#define VM_CH_REQ BIT(21)
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#define IP_TMR 0x05
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#define POWER_DELAY_CYCLE_256 0x80
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#define POWER_DELAY_CYCLE_64 0x40
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#define PVT_POLL_DELAY_US 20
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#define PVT_POLL_TIMEOUT_US 20000
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#define PVT_H_CONST 100000
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#define PVT_CAL5_CONST 2047
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#define PVT_G_CONST 40000
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#define PVT_CONV_BITS 10
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#define PVT_N_CONST 90
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#define PVT_R_CONST 245805
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struct pvt_device {
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struct regmap *c_map;
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struct regmap *t_map;
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struct regmap *p_map;
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struct regmap *v_map;
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struct clk *clk;
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struct reset_control *rst;
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u32 t_num;
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u32 p_num;
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u32 v_num;
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u32 ip_freq;
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u8 *vm_idx;
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};
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static umode_t pvt_is_visible(const void *data, enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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switch (type) {
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case hwmon_temp:
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if (attr == hwmon_temp_input)
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return 0444;
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break;
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case hwmon_in:
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if (attr == hwmon_in_input)
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return 0444;
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break;
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default:
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break;
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}
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return 0;
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}
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static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val)
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{
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struct pvt_device *pvt = dev_get_drvdata(dev);
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struct regmap *t_map = pvt->t_map;
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u32 stat, nbs;
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int ret;
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u64 tmp;
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switch (attr) {
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case hwmon_temp_input:
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ret = regmap_read_poll_timeout(t_map, SDIF_DONE(channel),
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stat, stat & SDIF_SMPL_DONE,
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PVT_POLL_DELAY_US,
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PVT_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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ret = regmap_read(t_map, SDIF_DATA(channel), &nbs);
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if(ret < 0)
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return ret;
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nbs &= SAMPLE_DATA_MSK;
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/*
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* Convert the register value to
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* degrees centigrade temperature
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*/
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tmp = nbs * PVT_H_CONST;
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do_div(tmp, PVT_CAL5_CONST);
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*val = tmp - PVT_G_CONST - pvt->ip_freq;
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val)
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{
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struct pvt_device *pvt = dev_get_drvdata(dev);
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struct regmap *v_map = pvt->v_map;
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u32 n, stat;
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u8 vm_idx;
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int ret;
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if (channel >= pvt->v_num)
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return -EINVAL;
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vm_idx = pvt->vm_idx[channel];
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switch (attr) {
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case hwmon_in_input:
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ret = regmap_read_poll_timeout(v_map, VM_SDIF_DONE(vm_idx),
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stat, stat & SDIF_SMPL_DONE,
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PVT_POLL_DELAY_US,
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PVT_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx), &n);
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if(ret < 0)
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return ret;
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n &= SAMPLE_DATA_MSK;
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/* Convert the N bitstream count into voltage */
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*val = (PVT_N_CONST * n - PVT_R_CONST) >> PVT_CONV_BITS;
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static int pvt_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *val)
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{
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switch (type) {
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case hwmon_temp:
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return pvt_read_temp(dev, attr, channel, val);
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case hwmon_in:
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return pvt_read_in(dev, attr, channel, val);
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default:
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return -EOPNOTSUPP;
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}
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}
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static const u32 pvt_chip_config[] = {
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HWMON_C_REGISTER_TZ,
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0
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};
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static const struct hwmon_channel_info pvt_chip = {
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.type = hwmon_chip,
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.config = pvt_chip_config,
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};
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static struct hwmon_channel_info pvt_temp = {
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.type = hwmon_temp,
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};
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static struct hwmon_channel_info pvt_in = {
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.type = hwmon_in,
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};
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static const struct hwmon_ops pvt_hwmon_ops = {
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.is_visible = pvt_is_visible,
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.read = pvt_read,
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};
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static struct hwmon_chip_info pvt_chip_info = {
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.ops = &pvt_hwmon_ops,
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};
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static int pvt_init(struct pvt_device *pvt)
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{
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u16 sys_freq, key, middle, low = 4, high = 8;
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struct regmap *t_map = pvt->t_map;
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struct regmap *p_map = pvt->p_map;
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struct regmap *v_map = pvt->v_map;
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u32 t_num = pvt->t_num;
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u32 p_num = pvt->p_num;
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u32 v_num = pvt->v_num;
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u32 clk_synth, val;
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int ret;
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sys_freq = clk_get_rate(pvt->clk) / HZ_PER_MHZ;
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while (high >= low) {
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middle = (low + high + 1) / 2;
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key = DIV_ROUND_CLOSEST(sys_freq, middle);
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if (key > CLK_SYS_CYCLES_MAX) {
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low = middle + 1;
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continue;
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} else if (key < CLK_SYS_CYCLES_MIN) {
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high = middle - 1;
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continue;
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} else {
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break;
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}
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}
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/*
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* The system supports 'clk_sys' to 'clk_ip' frequency ratios
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* from 2:1 to 512:1
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*/
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key = clamp_val(key, CLK_SYS_CYCLES_MIN, CLK_SYS_CYCLES_MAX) - 2;
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clk_synth = ((key + 1) >> 1) << CLK_SYNTH_LO_SFT |
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(key >> 1) << CLK_SYNTH_HI_SFT |
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(key >> 1) << CLK_SYNTH_HOLD_SFT | CLK_SYNTH_EN;
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pvt->ip_freq = sys_freq * 100 / (key + 2);
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if (t_num) {
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ret = regmap_write(t_map, SDIF_SMPL_CTRL, 0x0);
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if(ret < 0)
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return ret;
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ret = regmap_write(t_map, SDIF_HALT, 0x0);
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if(ret < 0)
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return ret;
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ret = regmap_write(t_map, CLK_SYNTH, clk_synth);
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if(ret < 0)
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return ret;
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ret = regmap_write(t_map, SDIF_DISABLE, 0x0);
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if(ret < 0)
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return ret;
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ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
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val, !(val & SDIF_BUSY),
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PVT_POLL_DELAY_US,
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PVT_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT |
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IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
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ret = regmap_write(t_map, SDIF_W, val);
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if(ret < 0)
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return ret;
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ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
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val, !(val & SDIF_BUSY),
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PVT_POLL_DELAY_US,
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PVT_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT |
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SDIF_WRN_W | SDIF_PROG;
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ret = regmap_write(t_map, SDIF_W, val);
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if(ret < 0)
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return ret;
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ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
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val, !(val & SDIF_BUSY),
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PVT_POLL_DELAY_US,
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PVT_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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val = IP_RST_REL | IP_RUN_CONT | IP_AUTO |
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IP_CTRL << SDIF_ADDR_SFT |
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SDIF_WRN_W | SDIF_PROG;
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ret = regmap_write(t_map, SDIF_W, val);
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if(ret < 0)
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return ret;
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}
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if (p_num) {
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ret = regmap_write(p_map, SDIF_HALT, 0x0);
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if(ret < 0)
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return ret;
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ret = regmap_write(p_map, SDIF_DISABLE, BIT(p_num) - 1);
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if(ret < 0)
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return ret;
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ret = regmap_write(p_map, CLK_SYNTH, clk_synth);
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if(ret < 0)
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return ret;
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}
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if (v_num) {
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ret = regmap_write(v_map, SDIF_SMPL_CTRL, 0x0);
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if(ret < 0)
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return ret;
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ret = regmap_write(v_map, SDIF_HALT, 0x0);
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if(ret < 0)
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return ret;
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ret = regmap_write(v_map, CLK_SYNTH, clk_synth);
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if(ret < 0)
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return ret;
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ret = regmap_write(v_map, SDIF_DISABLE, 0x0);
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if(ret < 0)
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return ret;
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ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
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val, !(val & SDIF_BUSY),
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PVT_POLL_DELAY_US,
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PVT_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT |
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CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT |
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SDIF_WRN_W | SDIF_PROG;
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ret = regmap_write(v_map, SDIF_W, val);
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if(ret < 0)
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return ret;
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ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
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val, !(val & SDIF_BUSY),
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PVT_POLL_DELAY_US,
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PVT_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT |
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SDIF_WRN_W | SDIF_PROG;
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ret = regmap_write(v_map, SDIF_W, val);
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if(ret < 0)
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return ret;
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ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
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val, !(val & SDIF_BUSY),
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PVT_POLL_DELAY_US,
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PVT_POLL_TIMEOUT_US);
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if (ret)
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return ret;
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val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE |
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IP_CTRL << SDIF_ADDR_SFT |
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SDIF_WRN_W | SDIF_PROG;
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ret = regmap_write(v_map, SDIF_W, val);
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct regmap_config pvt_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
};
|
||||
|
||||
static int pvt_get_regmap(struct platform_device *pdev, char *reg_name,
|
||||
struct pvt_device *pvt)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct regmap **reg_map;
|
||||
void __iomem *io_base;
|
||||
|
||||
if (!strcmp(reg_name, "common"))
|
||||
reg_map = &pvt->c_map;
|
||||
else if (!strcmp(reg_name, "ts"))
|
||||
reg_map = &pvt->t_map;
|
||||
else if (!strcmp(reg_name, "pd"))
|
||||
reg_map = &pvt->p_map;
|
||||
else if (!strcmp(reg_name, "vm"))
|
||||
reg_map = &pvt->v_map;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
io_base = devm_platform_ioremap_resource_byname(pdev, reg_name);
|
||||
if (IS_ERR(io_base))
|
||||
return PTR_ERR(io_base);
|
||||
|
||||
pvt_regmap_config.name = reg_name;
|
||||
*reg_map = devm_regmap_init_mmio(dev, io_base, &pvt_regmap_config);
|
||||
if (IS_ERR(*reg_map)) {
|
||||
dev_err(dev, "failed to init register map\n");
|
||||
return PTR_ERR(*reg_map);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pvt_clk_disable(void *data)
|
||||
{
|
||||
struct pvt_device *pvt = data;
|
||||
|
||||
clk_disable_unprepare(pvt->clk);
|
||||
}
|
||||
|
||||
static int pvt_clk_enable(struct device *dev, struct pvt_device *pvt)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(pvt->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return devm_add_action_or_reset(dev, pvt_clk_disable, pvt);
|
||||
}
|
||||
|
||||
static void pvt_reset_control_assert(void *data)
|
||||
{
|
||||
struct pvt_device *pvt = data;
|
||||
|
||||
reset_control_assert(pvt->rst);
|
||||
}
|
||||
|
||||
static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = reset_control_deassert(pvt->rst);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return devm_add_action_or_reset(dev, pvt_reset_control_assert, pvt);
|
||||
}
|
||||
|
||||
static int mr75203_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct hwmon_channel_info **pvt_info;
|
||||
u32 ts_num, vm_num, pd_num, val, index, i;
|
||||
struct device *dev = &pdev->dev;
|
||||
u32 *temp_config, *in_config;
|
||||
struct device *hwmon_dev;
|
||||
struct pvt_device *pvt;
|
||||
int ret;
|
||||
|
||||
pvt = devm_kzalloc(dev, sizeof(*pvt), GFP_KERNEL);
|
||||
if (!pvt)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = pvt_get_regmap(pdev, "common", pvt);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pvt->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(pvt->clk))
|
||||
return dev_err_probe(dev, PTR_ERR(pvt->clk), "failed to get clock\n");
|
||||
|
||||
ret = pvt_clk_enable(dev, pvt);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pvt->rst = devm_reset_control_get_exclusive(dev, NULL);
|
||||
if (IS_ERR(pvt->rst))
|
||||
return dev_err_probe(dev, PTR_ERR(pvt->rst),
|
||||
"failed to get reset control\n");
|
||||
|
||||
ret = pvt_reset_control_deassert(dev, pvt);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "cannot deassert reset control\n");
|
||||
|
||||
ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val);
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
|
||||
ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT;
|
||||
pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT;
|
||||
vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT;
|
||||
pvt->t_num = ts_num;
|
||||
pvt->p_num = pd_num;
|
||||
pvt->v_num = vm_num;
|
||||
val = 0;
|
||||
if (ts_num)
|
||||
val++;
|
||||
if (vm_num)
|
||||
val++;
|
||||
if (!val)
|
||||
return -ENODEV;
|
||||
|
||||
pvt_info = devm_kcalloc(dev, val + 2, sizeof(*pvt_info), GFP_KERNEL);
|
||||
if (!pvt_info)
|
||||
return -ENOMEM;
|
||||
pvt_info[0] = &pvt_chip;
|
||||
index = 1;
|
||||
|
||||
if (ts_num) {
|
||||
ret = pvt_get_regmap(pdev, "ts", pvt);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
temp_config = devm_kcalloc(dev, ts_num + 1,
|
||||
sizeof(*temp_config), GFP_KERNEL);
|
||||
if (!temp_config)
|
||||
return -ENOMEM;
|
||||
|
||||
memset32(temp_config, HWMON_T_INPUT, ts_num);
|
||||
pvt_temp.config = temp_config;
|
||||
pvt_info[index++] = &pvt_temp;
|
||||
}
|
||||
|
||||
if (pd_num) {
|
||||
ret = pvt_get_regmap(pdev, "pd", pvt);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (vm_num) {
|
||||
u32 num = vm_num;
|
||||
|
||||
ret = pvt_get_regmap(pdev, "vm", pvt);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pvt->vm_idx = devm_kcalloc(dev, vm_num, sizeof(*pvt->vm_idx),
|
||||
GFP_KERNEL);
|
||||
if (!pvt->vm_idx)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = device_property_read_u8_array(dev, "intel,vm-map",
|
||||
pvt->vm_idx, vm_num);
|
||||
if (ret) {
|
||||
num = 0;
|
||||
} else {
|
||||
for (i = 0; i < vm_num; i++)
|
||||
if (pvt->vm_idx[i] >= vm_num ||
|
||||
pvt->vm_idx[i] == 0xff) {
|
||||
num = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Incase intel,vm-map property is not defined, we assume
|
||||
* incremental channel numbers.
|
||||
*/
|
||||
for (i = num; i < vm_num; i++)
|
||||
pvt->vm_idx[i] = i;
|
||||
|
||||
in_config = devm_kcalloc(dev, num + 1,
|
||||
sizeof(*in_config), GFP_KERNEL);
|
||||
if (!in_config)
|
||||
return -ENOMEM;
|
||||
|
||||
memset32(in_config, HWMON_I_INPUT, num);
|
||||
in_config[num] = 0;
|
||||
pvt_in.config = in_config;
|
||||
|
||||
pvt_info[index++] = &pvt_in;
|
||||
}
|
||||
|
||||
ret = pvt_init(pvt);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to init pvt: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pvt_chip_info.info = pvt_info;
|
||||
hwmon_dev = devm_hwmon_device_register_with_info(dev, "pvt",
|
||||
pvt,
|
||||
&pvt_chip_info,
|
||||
NULL);
|
||||
|
||||
return PTR_ERR_OR_ZERO(hwmon_dev);
|
||||
}
|
||||
|
||||
static const struct of_device_id moortec_pvt_of_match[] = {
|
||||
{ .compatible = "moortec,mr75203" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, moortec_pvt_of_match);
|
||||
|
||||
static struct platform_driver moortec_pvt_driver = {
|
||||
.driver = {
|
||||
.name = "moortec-pvt",
|
||||
.of_match_table = moortec_pvt_of_match,
|
||||
},
|
||||
.probe = mr75203_probe,
|
||||
};
|
||||
module_platform_driver(moortec_pvt_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user