forked from luck/tmp_suning_uos_patched
ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate clean lines
This patch implements the work-around for the errata 588369.The secure API is used to alter L2 debug register because of trust-zone. This version updated with comments from Russell and Catalin and generated against 2.6.33-rc6 mainline kernel. Detail comments can be found: http://www.spinics.net/lists/linux-omap/msg23431.html Signed-off-by: Woodruff Richard <r-woodruff2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -924,6 +924,19 @@ config ARM_ERRATA_460075
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ACTLR register. Note that setting specific bits in the ACTLR register
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ACTLR register. Note that setting specific bits in the ACTLR register
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may not be available in non-secure mode.
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may not be available in non-secure mode.
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config PL310_ERRATA_588369
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bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
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depends on CACHE_L2X0 && ARCH_OMAP4
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help
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The PL310 L2 cache controller implements three types of Clean &
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Invalidate maintenance operations: by Physical Address
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(offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
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They are architecturally defined to behave as the execution of a
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clean operation followed immediately by an invalidate operation,
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both performing to the same memory location. This functionality
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is not correctly implemented in PL310 as clean lines are not
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invalidated as a result of these operations. Note that this errata
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uses Texas Instrument's secure monitor api.
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endmenu
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endmenu
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source "arch/arm/common/Kconfig"
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source "arch/arm/common/Kconfig"
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@ -56,12 +56,42 @@ static inline void l2x0_inv_line(unsigned long addr)
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writel(addr, base + L2X0_INV_LINE_PA);
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writel(addr, base + L2X0_INV_LINE_PA);
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}
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}
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#ifdef CONFIG_PL310_ERRATA_588369
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static void debug_writel(unsigned long val)
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{
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extern void omap_smc1(u32 fn, u32 arg);
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/*
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* Texas Instrument secure monitor api to modify the
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* PL310 Debug Control Register.
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*/
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omap_smc1(0x100, val);
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}
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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/* Clean by PA followed by Invalidate by PA */
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_LINE_PA);
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel(addr, base + L2X0_INV_LINE_PA);
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}
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#else
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/* Optimised out for non-errata case */
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static inline void debug_writel(unsigned long val)
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{
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}
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static inline void l2x0_flush_line(unsigned long addr)
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static inline void l2x0_flush_line(unsigned long addr)
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{
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{
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void __iomem *base = l2x0_base;
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
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writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
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}
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}
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#endif
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static inline void l2x0_inv_all(void)
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static inline void l2x0_inv_all(void)
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{
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{
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@ -83,13 +113,17 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
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spin_lock_irqsave(&l2x0_lock, flags);
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spin_lock_irqsave(&l2x0_lock, flags);
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if (start & (CACHE_LINE_SIZE - 1)) {
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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start &= ~(CACHE_LINE_SIZE - 1);
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debug_writel(0x03);
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l2x0_flush_line(start);
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l2x0_flush_line(start);
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debug_writel(0x00);
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start += CACHE_LINE_SIZE;
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start += CACHE_LINE_SIZE;
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}
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}
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if (end & (CACHE_LINE_SIZE - 1)) {
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if (end & (CACHE_LINE_SIZE - 1)) {
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end &= ~(CACHE_LINE_SIZE - 1);
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end &= ~(CACHE_LINE_SIZE - 1);
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debug_writel(0x03);
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l2x0_flush_line(end);
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l2x0_flush_line(end);
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debug_writel(0x00);
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}
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}
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while (start < end) {
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while (start < end) {
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@ -145,10 +179,12 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
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while (start < end) {
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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unsigned long blk_end = start + min(end - start, 4096UL);
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debug_writel(0x03);
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while (start < blk_end) {
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while (start < blk_end) {
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l2x0_flush_line(start);
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l2x0_flush_line(start);
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start += CACHE_LINE_SIZE;
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start += CACHE_LINE_SIZE;
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}
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}
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debug_writel(0x00);
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if (blk_end < end) {
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if (blk_end < end) {
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spin_unlock_irqrestore(&l2x0_lock, flags);
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spin_unlock_irqrestore(&l2x0_lock, flags);
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