forked from luck/tmp_suning_uos_patched
ARM: S5PC1XX: clock registers rename
S5PC100 and S5PC110 clock registers differs in many places, rename all previously defined registers to be S5PC100 specific. Remove all power management registers. They will be added later to a separate file. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Kyungmin Park
Ben Dooks
parent
b0cc3031ff
commit
9ebaf2f4e7
@ -13,68 +13,69 @@
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#ifndef __PLAT_REGS_CLOCK_H
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#define __PLAT_REGS_CLOCK_H __FILE__
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#define S5PC1XX_CLKREG(x) (S5PC1XX_VA_CLK + (x))
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#define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x))
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#define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x))
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#define S5PC1XX_APLL_LOCK S5PC1XX_CLKREG(0x00)
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#define S5PC1XX_MPLL_LOCK S5PC1XX_CLKREG(0x04)
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#define S5PC1XX_EPLL_LOCK S5PC1XX_CLKREG(0x08)
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#define S5PC100_HPLL_LOCK S5PC1XX_CLKREG(0x0C)
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/* s5pc100 register for clock */
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#define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00)
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#define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04)
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#define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08)
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#define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C)
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#define S5PC1XX_APLL_CON S5PC1XX_CLKREG(0x100)
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#define S5PC1XX_MPLL_CON S5PC1XX_CLKREG(0x104)
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#define S5PC1XX_EPLL_CON S5PC1XX_CLKREG(0x108)
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#define S5PC100_HPLL_CON S5PC1XX_CLKREG(0x10C)
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#define S5PC100_APLL_CON S5PC100_CLKREG(0x100)
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#define S5PC100_MPLL_CON S5PC100_CLKREG(0x104)
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#define S5PC100_EPLL_CON S5PC100_CLKREG(0x108)
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#define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C)
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#define S5PC1XX_CLK_SRC0 S5PC1XX_CLKREG(0x200)
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#define S5PC1XX_CLK_SRC1 S5PC1XX_CLKREG(0x204)
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#define S5PC1XX_CLK_SRC2 S5PC1XX_CLKREG(0x208)
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#define S5PC1XX_CLK_SRC3 S5PC1XX_CLKREG(0x20C)
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#define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200)
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#define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204)
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#define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208)
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#define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C)
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#define S5PC1XX_CLK_DIV0 S5PC1XX_CLKREG(0x300)
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#define S5PC1XX_CLK_DIV1 S5PC1XX_CLKREG(0x304)
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#define S5PC1XX_CLK_DIV2 S5PC1XX_CLKREG(0x308)
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#define S5PC1XX_CLK_DIV3 S5PC1XX_CLKREG(0x30C)
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#define S5PC1XX_CLK_DIV4 S5PC1XX_CLKREG(0x310)
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#define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300)
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#define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304)
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#define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308)
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#define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C)
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#define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310)
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#define S5PC100_CLK_OUT S5PC1XX_CLKREG(0x400)
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#define S5PC100_CLK_OUT S5PC100_CLKREG(0x400)
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#define S5PC100_CLKGATE_D00 S5PC1XX_CLKREG(0x500)
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#define S5PC100_CLKGATE_D01 S5PC1XX_CLKREG(0x504)
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#define S5PC100_CLKGATE_D02 S5PC1XX_CLKREG(0x508)
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#define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500)
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#define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504)
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#define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508)
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#define S5PC100_CLKGATE_D10 S5PC1XX_CLKREG(0x520)
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#define S5PC100_CLKGATE_D11 S5PC1XX_CLKREG(0x524)
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#define S5PC100_CLKGATE_D12 S5PC1XX_CLKREG(0x528)
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#define S5PC100_CLKGATE_D13 S5PC1XX_CLKREG(0x52C)
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#define S5PC100_CLKGATE_D14 S5PC1XX_CLKREG(0x530)
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#define S5PC100_CLKGATE_D15 S5PC1XX_CLKREG(0x534)
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#define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520)
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#define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524)
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#define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528)
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#define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C)
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#define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530)
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#define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534)
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#define S5PC100_CLKGATE_D20 S5PC1XX_CLKREG(0x540)
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#define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540)
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#define S5PC100_SCLKGATE0 S5PC1XX_CLKREG(0x560)
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#define S5PC100_SCLKGATE1 S5PC1XX_CLKREG(0x564)
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#define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560)
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#define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564)
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#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200)
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#define S5PC1XX_EPLL_EN (1<<31)
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#define S5PC1XX_EPLL_MASK 0xffffffff
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#define S5PC1XX_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
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/* EPLL_CON */
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#define S5PC100_EPLL_EN (1<<31)
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#define S5PC100_EPLL_MASK 0xffffffff
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#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
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/* CLKSRC0 */
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#define S5PC1XX_CLKSRC0_APLL_MASK (0x1<<0)
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#define S5PC1XX_CLKSRC0_APLL_SHIFT (0)
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#define S5PC1XX_CLKSRC0_MPLL_MASK (0x1<<4)
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#define S5PC1XX_CLKSRC0_MPLL_SHIFT (4)
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#define S5PC1XX_CLKSRC0_EPLL_MASK (0x1<<8)
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#define S5PC1XX_CLKSRC0_EPLL_SHIFT (8)
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#define S5PC100_CLKSRC0_APLL_MASK (0x1<<0)
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#define S5PC100_CLKSRC0_APLL_SHIFT (0)
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#define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4)
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#define S5PC100_CLKSRC0_MPLL_SHIFT (4)
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#define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8)
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#define S5PC100_CLKSRC0_EPLL_SHIFT (8)
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#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12)
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#define S5PC100_CLKSRC0_HPLL_SHIFT (12)
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#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16)
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#define S5PC100_CLKSRC0_AMMUX_SHIFT (16)
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#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20)
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#define S5PC100_CLKSRC0_HREF_SHIFT (20)
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#define S5PC1XX_CLKSRC0_ONENAND_MASK (0x1<<24)
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#define S5PC1XX_CLKSRC0_ONENAND_SHIFT (24)
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#define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24)
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#define S5PC100_CLKSRC0_ONENAND_SHIFT (24)
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/* CLKSRC1 */
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@ -127,10 +128,9 @@
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#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24)
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#define S5PC100_CLKSRC3_SPDIF_SHIFT (24)
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/* CLKDIV0 */
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#define S5PC1XX_CLKDIV0_APLL_MASK (0x1<<0)
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#define S5PC1XX_CLKDIV0_APLL_SHIFT (0)
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#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
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#define S5PC100_CLKDIV0_APLL_SHIFT (0)
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#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
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#define S5PC100_CLKDIV0_ARM_SHIFT (4)
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#define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
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@ -141,8 +141,8 @@
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#define S5PC100_CLKDIV0_SECSS_SHIFT (16)
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/* CLKDIV1 */
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#define S5PC100_CLKDIV1_AM_MASK (0x7<<0)
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#define S5PC100_CLKDIV1_AM_SHIFT (0)
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#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
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#define S5PC100_CLKDIV1_APLL2_SHIFT (0)
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#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
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#define S5PC100_CLKDIV1_MPLL_SHIFT (4)
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#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
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@ -202,7 +202,6 @@
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#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20)
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#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20)
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/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
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#define S5PC100_CLKGATE_D00_INTC (1<<0)
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#define S5PC100_CLKGATE_D00_TZIC (1<<1)
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@ -295,8 +294,8 @@
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#define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
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/* Special Clock Gate 0 Registers */
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#define S5PC1XX_CLKGATE_SCLK0_HPM (1<<0)
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#define S5PC1XX_CLKGATE_SCLK0_PWI (1<<1)
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#define S5PC100_CLKGATE_SCLK0_HPM (1<<0)
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#define S5PC100_CLKGATE_SCLK0_PWI (1<<1)
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#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
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#define S5PC100_CLKGATE_SCLK0_UART (1<<3)
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#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
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@ -329,89 +328,28 @@
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#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
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#define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
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/* register for power management */
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#define S5PC100_PWR_CFG S5PC1XX_CLKREG(0x8000)
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#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_CLKREG(0x8004)
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#define S5PC100_NORMAL_CFG S5PC1XX_CLKREG(0x8010)
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#define S5PC100_STOP_CFG S5PC1XX_CLKREG(0x8014)
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#define S5PC100_SLEEP_CFG S5PC1XX_CLKREG(0x8018)
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#define S5PC100_STOP_MEM_CFG S5PC1XX_CLKREG(0x801C)
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#define S5PC100_OSC_FREQ S5PC1XX_CLKREG(0x8100)
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#define S5PC100_OSC_STABLE S5PC1XX_CLKREG(0x8104)
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#define S5PC100_PWR_STABLE S5PC1XX_CLKREG(0x8108)
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#define S5PC100_MTC_STABLE S5PC1XX_CLKREG(0x8110)
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#define S5PC100_CLAMP_STABLE S5PC1XX_CLKREG(0x8114)
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#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200)
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#define S5PC100_RST_STAT S5PC1XX_CLKREG(0x8300)
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#define S5PC100_WAKEUP_STAT S5PC1XX_CLKREG(0x8304)
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#define S5PC100_BLK_PWR_STAT S5PC1XX_CLKREG(0x8308)
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#define S5PC100_INFORM0 S5PC1XX_CLKREG(0x8400)
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#define S5PC100_INFORM1 S5PC1XX_CLKREG(0x8404)
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#define S5PC100_INFORM2 S5PC1XX_CLKREG(0x8408)
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#define S5PC100_INFORM3 S5PC1XX_CLKREG(0x840C)
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#define S5PC100_INFORM4 S5PC1XX_CLKREG(0x8410)
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#define S5PC100_INFORM5 S5PC1XX_CLKREG(0x8414)
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#define S5PC100_INFORM6 S5PC1XX_CLKREG(0x8418)
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#define S5PC100_INFORM7 S5PC1XX_CLKREG(0x841C)
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#define S5PC100_DCGIDX_MAP0 S5PC1XX_CLKREG(0x8500)
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#define S5PC100_DCGIDX_MAP1 S5PC1XX_CLKREG(0x8504)
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#define S5PC100_DCGIDX_MAP2 S5PC1XX_CLKREG(0x8508)
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#define S5PC100_DCGPERF_MAP0 S5PC1XX_CLKREG(0x850C)
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#define S5PC100_DCGPERF_MAP1 S5PC1XX_CLKREG(0x8510)
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#define S5PC100_DVCIDX_MAP S5PC1XX_CLKREG(0x8514)
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#define S5PC100_FREQ_CPU S5PC1XX_CLKREG(0x8518)
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#define S5PC100_FREQ_DPM S5PC1XX_CLKREG(0x851C)
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#define S5PC100_DVSEMCLK_EN S5PC1XX_CLKREG(0x8520)
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#define S5PC100_APLL_CON_L8 S5PC1XX_CLKREG(0x8600)
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#define S5PC100_APLL_CON_L7 S5PC1XX_CLKREG(0x8604)
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#define S5PC100_APLL_CON_L6 S5PC1XX_CLKREG(0x8608)
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#define S5PC100_APLL_CON_L5 S5PC1XX_CLKREG(0x860C)
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#define S5PC100_APLL_CON_L4 S5PC1XX_CLKREG(0x8610)
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#define S5PC100_APLL_CON_L3 S5PC1XX_CLKREG(0x8614)
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#define S5PC100_APLL_CON_L2 S5PC1XX_CLKREG(0x8618)
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#define S5PC100_APLL_CON_L1 S5PC1XX_CLKREG(0x861C)
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#define S5PC100_IEM_CONTROL S5PC1XX_CLKREG(0x8620)
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#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_CLKREG(0x8700)
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#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_CLKREG(0x8704)
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#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_CLKREG(0x8708)
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#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_CLKREG(0x870C)
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#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_CLKREG(0x8710)
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#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_CLKREG(0x8714)
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#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_CLKREG(0x8718)
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#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_CLKREG(0x871C)
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#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_CLKREG(0x8724)
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#define S5PC100_SWRESET S5PC1XX_CLKREG(0x100000)
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#define S5PC100_OND_SWRESET S5PC1XX_CLKREG(0x100008)
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#define S5PC100_GEN_CTRL S5PC1XX_CLKREG(0x100100)
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#define S5PC100_GEN_STATUS S5PC1XX_CLKREG(0x100104)
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#define S5PC100_MEM_SYS_CFG S5PC1XX_CLKREG(0x100200)
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#define S5PC100_CAM_MUX_SEL S5PC1XX_CLKREG(0x100300)
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#define S5PC100_MIXER_OUT_SEL S5PC1XX_CLKREG(0x100304)
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#define S5PC100_LPMP_MODE_SEL S5PC1XX_CLKREG(0x100308)
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#define S5PC100_MIPI_PHY_CON0 S5PC1XX_CLKREG(0x100400)
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#define S5PC100_MIPI_PHY_CON1 S5PC1XX_CLKREG(0x100414)
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#define S5PC100_HDMI_PHY_CON0 S5PC1XX_CLKREG(0x100420)
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#define S5PC100_CFG_WFI_CLEAN (~(3<<5))
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#define S5PC100_CFG_WFI_IDLE (1<<5)
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#define S5PC100_CFG_WFI_STOP (2<<5)
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#define S5PC100_CFG_WFI_SLEEP (3<<5)
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#define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000)
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#define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008)
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#define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100)
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#define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104)
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#define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200)
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#define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300)
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#define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304)
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#define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308)
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#define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400)
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#define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414)
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#define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420)
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#define S5PC100_SWRESET_RESETVAL 0xc100
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#define S5PC100_OTHER_SYS_INT 24
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#define S5PC100_OTHER_STA_TYPE 23
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#define STA_TYPE_EXPON 0
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#define STA_TYPE_SFR 1
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#define S5PC100_PWR_STA_EXP_SCALE 0
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#define S5PC100_PWR_STA_CNT 4
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#define S5PC100_PWR_STABLE_COUNT 85500
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#define S5PC100_SLEEP_CFG_OSC_EN 0
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/* OTHERS Resgister */
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#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
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#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
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#define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28)
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/* MIPI D-PHY Control Register 0 */
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@ -87,13 +87,13 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
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/* can't rely on clock lock, this register has other usages */
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local_irq_save(flags);
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val = __raw_readl(S5PC1XX_CLK_SRC1);
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val = __raw_readl(S5PC100_CLKSRC1);
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if (enable)
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val |= S5PC100_CLKSRC1_CLK48M_MASK;
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else
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val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
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__raw_writel(val, S5PC1XX_CLK_SRC1);
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__raw_writel(val, S5PC100_CLKSRC1);
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local_irq_restore(flags);
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return 0;
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@ -685,7 +685,7 @@ static struct clk init_clocks[] = {
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.id = -1,
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.parent = NULL,
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.enable = s5pc1xx_sclk0_ctrl,
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.ctrlbit = S5PC1XX_CLKGATE_SCLK0_HPM,
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.ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
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}, {
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.name = "sclk_onenand",
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.id = -1,
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@ -801,10 +801,10 @@ static struct clksrc_clk clk_mout_apll = {
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.name = "mout_apll",
|
||||
.id = -1,
|
||||
},
|
||||
.shift = S5PC1XX_CLKSRC0_APLL_SHIFT,
|
||||
.mask = S5PC1XX_CLKSRC0_APLL_MASK,
|
||||
.shift = S5PC100_CLKSRC0_APLL_SHIFT,
|
||||
.mask = S5PC100_CLKSRC0_APLL_MASK,
|
||||
.sources = &clk_src_apll,
|
||||
.reg_source = S5PC1XX_CLK_SRC0,
|
||||
.reg_source = S5PC100_CLKSRC0,
|
||||
};
|
||||
|
||||
static struct clk clk_fout_epll = {
|
||||
@ -827,10 +827,10 @@ static struct clksrc_clk clk_mout_epll = {
|
||||
.name = "mout_epll",
|
||||
.id = -1,
|
||||
},
|
||||
.shift = S5PC1XX_CLKSRC0_EPLL_SHIFT,
|
||||
.mask = S5PC1XX_CLKSRC0_EPLL_MASK,
|
||||
.shift = S5PC100_CLKSRC0_EPLL_SHIFT,
|
||||
.mask = S5PC100_CLKSRC0_EPLL_MASK,
|
||||
.sources = &clk_src_epll,
|
||||
.reg_source = S5PC1XX_CLK_SRC0,
|
||||
.reg_source = S5PC100_CLKSRC0,
|
||||
};
|
||||
|
||||
static struct clk *clk_src_mpll_list[] = {
|
||||
@ -848,10 +848,10 @@ static struct clksrc_clk clk_mout_mpll = {
|
||||
.name = "mout_mpll",
|
||||
.id = -1,
|
||||
},
|
||||
.shift = S5PC1XX_CLKSRC0_MPLL_SHIFT,
|
||||
.mask = S5PC1XX_CLKSRC0_MPLL_MASK,
|
||||
.shift = S5PC100_CLKSRC0_MPLL_SHIFT,
|
||||
.mask = S5PC100_CLKSRC0_MPLL_MASK,
|
||||
.sources = &clk_src_mpll,
|
||||
.reg_source = S5PC1XX_CLK_SRC0,
|
||||
.reg_source = S5PC100_CLKSRC0,
|
||||
};
|
||||
|
||||
static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
|
||||
@ -861,7 +861,7 @@ static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
|
||||
|
||||
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
|
||||
|
||||
clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK;
|
||||
clkdiv = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK;
|
||||
rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1;
|
||||
|
||||
return rate;
|
||||
@ -881,7 +881,7 @@ static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk)
|
||||
|
||||
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
|
||||
|
||||
clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
|
||||
clkdiv = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
|
||||
rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
|
||||
|
||||
return rate;
|
||||
@ -1007,8 +1007,8 @@ static struct clksrc_clk clk_uart_uclk1 = {
|
||||
.mask = S5PC100_CLKSRC1_UART_MASK,
|
||||
.sources = &clkset_uart,
|
||||
.divider_shift = S5PC100_CLKDIV2_UART_SHIFT,
|
||||
.reg_divider = S5PC1XX_CLK_DIV2,
|
||||
.reg_source = S5PC1XX_CLK_SRC1,
|
||||
.reg_divider = S5PC100_CLKDIV2,
|
||||
.reg_source = S5PC100_CLKSRC1,
|
||||
};
|
||||
|
||||
/* Clock initialisation code */
|
||||
@ -1061,8 +1061,8 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
|
||||
|
||||
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
|
||||
|
||||
clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0);
|
||||
clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1);
|
||||
clkdiv0 = __raw_readl(S5PC100_CLKDIV0);
|
||||
clkdiv1 = __raw_readl(S5PC100_CLKDIV1);
|
||||
|
||||
printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
|
||||
__func__, clkdiv0, clkdiv1);
|
||||
@ -1075,15 +1075,15 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
|
||||
|
||||
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
|
||||
|
||||
apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON));
|
||||
mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON));
|
||||
epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON));
|
||||
apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
|
||||
mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
|
||||
epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
|
||||
hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
|
||||
|
||||
printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n",
|
||||
apll, mpll, epll, hpll);
|
||||
|
||||
armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL);
|
||||
armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL);
|
||||
armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
|
||||
hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
|
||||
pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user