forked from luck/tmp_suning_uos_patched
Merge branch 'linus' into irq/core
Get the urgent fixes from upstream to avoid conflicts.
This commit is contained in:
Thomas Gleixner
commit
9f61f62544
7
CREDITS
7
CREDITS
|
|
@ -3709,6 +3709,13 @@ N: Dirk Verworner
|
|||
D: Co-author of German book ``Linux-Kernel-Programmierung''
|
||||
D: Co-founder of Berlin Linux User Group
|
||||
|
||||
N: Andrew Victor
|
||||
E: linux@maxim.org.za
|
||||
W: http://maxim.org.za/at91_26.html
|
||||
D: First maintainer of Atmel ARM-based SoC, aka AT91
|
||||
D: Introduced support for at91rm9200, the first chip of AT91 family
|
||||
S: South Africa
|
||||
|
||||
N: Riku Voipio
|
||||
E: riku.voipio@iki.fi
|
||||
D: Author of PCA9532 LED and Fintek f75375s hwmon driver
|
||||
|
|
|
|||
|
|
@ -505,7 +505,10 @@ at module load time (for a module) with:
|
|||
|
||||
The addresses are normal I2C addresses. The adapter is the string
|
||||
name of the adapter, as shown in /sys/class/i2c-adapter/i2c-<n>/name.
|
||||
It is *NOT* i2c-<n> itself.
|
||||
It is *NOT* i2c-<n> itself. Also, the comparison is done ignoring
|
||||
spaces, so if the name is "This is an I2C chip" you can say
|
||||
adapter_name=ThisisanI2cchip. This is because it's hard to pass in
|
||||
spaces in kernel parameters.
|
||||
|
||||
The debug flags are bit flags for each BMC found, they are:
|
||||
IPMI messages: 1, driver state: 2, timing: 4, I2C probe: 8
|
||||
|
|
|
|||
|
|
@ -253,7 +253,7 @@ input driver:
|
|||
GPIO support
|
||||
~~~~~~~~~~~~
|
||||
ACPI 5 introduced two new resources to describe GPIO connections: GpioIo
|
||||
and GpioInt. These resources are used be used to pass GPIO numbers used by
|
||||
and GpioInt. These resources can be used to pass GPIO numbers used by
|
||||
the device to the driver. ACPI 5.1 extended this with _DSD (Device
|
||||
Specific Data) which made it possible to name the GPIOs among other things.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
_DSD Device Properties Related to GPIO
|
||||
--------------------------------------
|
||||
|
||||
With the release of ACPI 5.1 and the _DSD configuration objecte names
|
||||
can finally be given to GPIOs (and other things as well) returned by
|
||||
_CRS. Previously, we were only able to use an integer index to find
|
||||
With the release of ACPI 5.1, the _DSD configuration object finally
|
||||
allows names to be given to GPIOs (and other things as well) returned
|
||||
by _CRS. Previously, we were only able to use an integer index to find
|
||||
the corresponding GPIO, which is pretty error prone (it depends on
|
||||
the _CRS output ordering, for example).
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ provided by Arteris.
|
|||
Required properties:
|
||||
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
|
||||
Should be "ti,omap4-l3-noc" for OMAP4 family
|
||||
Should be "ti,omap5-l3-noc" for OMAP5 family
|
||||
Should be "ti,dra7-l3-noc" for DRA7 family
|
||||
Should be "ti,am4372-l3-noc" for AM43 family
|
||||
- reg: Contains L3 register address range for each noc domain.
|
||||
|
|
|
|||
|
|
@ -17,7 +17,8 @@ Required properties:
|
|||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock
|
||||
handles, shall be xtal reference clock or xtal and clkin for
|
||||
si5351c only.
|
||||
si5351c only. Corresponding clock input names are "xtal" and
|
||||
"clkin" respectively.
|
||||
- #address-cells: shall be set to 1.
|
||||
- #size-cells: shall be set to 0.
|
||||
|
||||
|
|
@ -71,6 +72,7 @@ i2c-master-node {
|
|||
|
||||
/* connect xtal input to 25MHz reference */
|
||||
clocks = <&ref25>;
|
||||
clock-names = "xtal";
|
||||
|
||||
/* connect xtal input as source of pll0 and pll1 */
|
||||
silabs,pll-source = <0 0>, <1 0>;
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ dma_apbx: dma-apbx@80024000 {
|
|||
80 81 68 69
|
||||
70 71 72 73
|
||||
74 75 76 77>;
|
||||
interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
|
||||
interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
|
||||
"saif0", "saif1", "i2c0", "i2c1",
|
||||
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
|
||||
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ Required properties:
|
|||
is not Linux-only, but in case of Linux, see the "m25p_ids"
|
||||
table in drivers/mtd/devices/m25p80.c for the list of supported
|
||||
chips.
|
||||
Must also include "nor-jedec" for any SPI NOR flash that can be
|
||||
identified by the JEDEC READ ID opcode (0x9F).
|
||||
Must also include "jedec,spi-nor" for any SPI NOR flash that can
|
||||
be identified by the JEDEC READ ID opcode (0x9F).
|
||||
- reg : Chip-Select number
|
||||
- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
|
||||
|
||||
|
|
@ -25,7 +25,7 @@ Example:
|
|||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80", "nor-jedec";
|
||||
compatible = "spansion,m25p80", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
m25p,fast-read;
|
||||
|
|
@ -3,7 +3,8 @@
|
|||
Required properties:
|
||||
- compatible: Should be "cdns,[<chip>-]{emac}"
|
||||
Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
|
||||
or the generic form: "cdns,emac".
|
||||
Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
|
||||
Or the generic form: "cdns,emac".
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupts: Should contain macb interrupt
|
||||
- phy-mode: see ethernet.txt file in the same directory.
|
||||
|
|
|
|||
30
Documentation/devicetree/bindings/rtc/abracon,abx80x.txt
Normal file
30
Documentation/devicetree/bindings/rtc/abracon,abx80x.txt
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
Abracon ABX80X I2C ultra low power RTC/Alarm chip
|
||||
|
||||
The Abracon ABX80X family consist of the ab0801, ab0803, ab0804, ab0805, ab1801,
|
||||
ab1803, ab1804 and ab1805. The ab0805 is the superset of ab080x and the ab1805
|
||||
is the superset of ab180x.
|
||||
|
||||
Required properties:
|
||||
|
||||
- "compatible": should one of:
|
||||
"abracon,abx80x"
|
||||
"abracon,ab0801"
|
||||
"abracon,ab0803"
|
||||
"abracon,ab0804"
|
||||
"abracon,ab0805"
|
||||
"abracon,ab1801"
|
||||
"abracon,ab1803"
|
||||
"abracon,ab1804"
|
||||
"abracon,ab1805"
|
||||
Using "abracon,abx80x" will enable chip autodetection.
|
||||
- "reg": I2C bus address of the device
|
||||
|
||||
Optional properties:
|
||||
|
||||
The abx804 and abx805 have a trickle charger that is able to charge the
|
||||
connected battery or supercap. Both the following properties have to be defined
|
||||
and valid to enable charging:
|
||||
|
||||
- "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V)
|
||||
- "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output
|
||||
resistor, the other values are in ohm.
|
||||
|
|
@ -9,7 +9,9 @@ a fast and comprehensive solution for finding use-after-free and out-of-bounds
|
|||
bugs.
|
||||
|
||||
KASan uses compile-time instrumentation for checking every memory access,
|
||||
therefore you will need a certain version of GCC > 4.9.2
|
||||
therefore you will need a gcc version of 4.9.2 or later. KASan could detect out
|
||||
of bounds accesses to stack or global variables, but only if gcc 5.0 or later was
|
||||
used to built the kernel.
|
||||
|
||||
Currently KASan is supported only for x86_64 architecture and requires that the
|
||||
kernel be built with the SLUB allocator.
|
||||
|
|
@ -23,8 +25,8 @@ To enable KASAN configure kernel with:
|
|||
|
||||
and choose between CONFIG_KASAN_OUTLINE and CONFIG_KASAN_INLINE. Outline/inline
|
||||
is compiler instrumentation types. The former produces smaller binary the
|
||||
latter is 1.1 - 2 times faster. Inline instrumentation requires GCC 5.0 or
|
||||
latter.
|
||||
latter is 1.1 - 2 times faster. Inline instrumentation requires a gcc version
|
||||
of 5.0 or later.
|
||||
|
||||
Currently KASAN works only with the SLUB memory allocator.
|
||||
For better bug detection and nicer report, enable CONFIG_STACKTRACE and put
|
||||
|
|
|
|||
|
|
@ -198,6 +198,9 @@ TTY_IO_ERROR If set, causes all subsequent userspace read/write
|
|||
|
||||
TTY_OTHER_CLOSED Device is a pty and the other side has closed.
|
||||
|
||||
TTY_OTHER_DONE Device is a pty and the other side has closed and
|
||||
all pending input processing has been completed.
|
||||
|
||||
TTY_NO_WRITE_SPLIT Prevent driver from splitting up writes into
|
||||
smaller chunks.
|
||||
|
||||
|
|
|
|||
|
|
@ -169,6 +169,10 @@ Shadow pages contain the following information:
|
|||
Contains the value of cr4.smep && !cr0.wp for which the page is valid
|
||||
(pages for which this is true are different from other pages; see the
|
||||
treatment of cr0.wp=0 below).
|
||||
role.smap_andnot_wp:
|
||||
Contains the value of cr4.smap && !cr0.wp for which the page is valid
|
||||
(pages for which this is true are different from other pages; see the
|
||||
treatment of cr0.wp=0 below).
|
||||
gfn:
|
||||
Either the guest page table containing the translations shadowed by this
|
||||
page, or the base page frame for linear translations. See role.direct.
|
||||
|
|
@ -344,10 +348,16 @@ on fault type:
|
|||
|
||||
(user write faults generate a #PF)
|
||||
|
||||
In the first case there is an additional complication if CR4.SMEP is
|
||||
enabled: since we've turned the page into a kernel page, the kernel may now
|
||||
execute it. We handle this by also setting spte.nx. If we get a user
|
||||
fetch or read fault, we'll change spte.u=1 and spte.nx=gpte.nx back.
|
||||
In the first case there are two additional complications:
|
||||
- if CR4.SMEP is enabled: since we've turned the page into a kernel page,
|
||||
the kernel may now execute it. We handle this by also setting spte.nx.
|
||||
If we get a user fetch or read fault, we'll change spte.u=1 and
|
||||
spte.nx=gpte.nx back.
|
||||
- if CR4.SMAP is disabled: since the page has been changed to a kernel
|
||||
page, it can not be reused when CR4.SMAP is enabled. We set
|
||||
CR4.SMAP && !CR0.WP into shadow page's role to avoid this case. Note,
|
||||
here we do not care the case that CR4.SMAP is enabled since KVM will
|
||||
directly inject #PF to guest due to failed permission check.
|
||||
|
||||
To prevent an spte that was converted into a kernel page with cr0.wp=0
|
||||
from being written by the kernel after cr0.wp has changed to 1, we make
|
||||
|
|
|
|||
76
MAINTAINERS
76
MAINTAINERS
|
|
@ -892,11 +892,10 @@ S: Maintained
|
|||
F: arch/arm/mach-alpine/
|
||||
|
||||
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
|
||||
M: Andrew Victor <linux@maxim.org.za>
|
||||
M: Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
|
||||
M: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://maxim.org.za/at91_26.html
|
||||
W: http://www.linux4sam.org
|
||||
S: Supported
|
||||
F: arch/arm/mach-at91/
|
||||
|
|
@ -975,7 +974,7 @@ S: Maintained
|
|||
ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
|
||||
M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
T: git git://git.berlios.de/gemini-board
|
||||
T: git git://github.com/ulli-kroll/linux.git
|
||||
S: Maintained
|
||||
F: arch/arm/mach-gemini/
|
||||
|
||||
|
|
@ -990,6 +989,12 @@ F: drivers/clocksource/timer-prima2.c
|
|||
F: drivers/clocksource/timer-atlas7.c
|
||||
N: [^a-z]sirf
|
||||
|
||||
ARM/CONEXANT DIGICOLOR MACHINE SUPPORT
|
||||
M: Baruch Siach <baruch@tkos.co.il>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
N: digicolor
|
||||
|
||||
ARM/EBSA110 MACHINE SUPPORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -1188,7 +1193,7 @@ ARM/MAGICIAN MACHINE SUPPORT
|
|||
M: Philipp Zabel <philipp.zabel@gmail.com>
|
||||
S: Maintained
|
||||
|
||||
ARM/Marvell Armada 370 and Armada XP SOC support
|
||||
ARM/Marvell Kirkwood and Armada 370, 375, 38x, XP SOC support
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
M: Gregory Clement <gregory.clement@free-electrons.com>
|
||||
|
|
@ -1197,12 +1202,17 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
|||
S: Maintained
|
||||
F: arch/arm/mach-mvebu/
|
||||
F: drivers/rtc/rtc-armada38x.c
|
||||
F: arch/arm/boot/dts/armada*
|
||||
F: arch/arm/boot/dts/kirkwood*
|
||||
|
||||
|
||||
ARM/Marvell Berlin SoC support
|
||||
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-berlin/
|
||||
F: arch/arm/boot/dts/berlin*
|
||||
|
||||
|
||||
ARM/Marvell Dove/MV78xx0/Orion SOC support
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
|
|
@ -1215,6 +1225,9 @@ F: arch/arm/mach-dove/
|
|||
F: arch/arm/mach-mv78xx0/
|
||||
F: arch/arm/mach-orion5x/
|
||||
F: arch/arm/plat-orion/
|
||||
F: arch/arm/boot/dts/dove*
|
||||
F: arch/arm/boot/dts/orion5x*
|
||||
|
||||
|
||||
ARM/Orion SoC/Technologic Systems TS-78xx platform support
|
||||
M: Alexander Clouter <alex@digriz.org.uk>
|
||||
|
|
@ -1366,6 +1379,7 @@ N: rockchip
|
|||
|
||||
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
|
||||
M: Kukjin Kim <kgene@kernel.org>
|
||||
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
|
@ -1439,9 +1453,10 @@ ARM/SOCFPGA ARCHITECTURE
|
|||
M: Dinh Nguyen <dinguyen@opensource.altera.com>
|
||||
S: Maintained
|
||||
F: arch/arm/mach-socfpga/
|
||||
F: arch/arm/boot/dts/socfpga*
|
||||
F: arch/arm/configs/socfpga_defconfig
|
||||
W: http://www.rocketboards.org
|
||||
T: git://git.rocketboards.org/linux-socfpga.git
|
||||
T: git://git.rocketboards.org/linux-socfpga-next.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
|
||||
|
||||
ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
|
||||
M: Dinh Nguyen <dinguyen@opensource.altera.com>
|
||||
|
|
@ -1929,7 +1944,7 @@ S: Maintained
|
|||
F: drivers/net/wireless/b43legacy/
|
||||
|
||||
BACKLIGHT CLASS/SUBSYSTEM
|
||||
M: Jingoo Han <jg1.han@samsung.com>
|
||||
M: Jingoo Han <jingoohan1@gmail.com>
|
||||
M: Lee Jones <lee.jones@linaro.org>
|
||||
S: Maintained
|
||||
F: drivers/video/backlight/
|
||||
|
|
@ -2116,8 +2131,9 @@ S: Supported
|
|||
F: drivers/net/ethernet/broadcom/bnx2x/
|
||||
|
||||
BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
|
||||
M: Christian Daudt <bcm@fixthebug.org>
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
M: Ray Jui <rjui@broadcom.com>
|
||||
M: Scott Branden <sbranden@broadcom.com>
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
T: git git://github.com/broadcom/mach-bcm
|
||||
S: Maintained
|
||||
|
|
@ -2168,7 +2184,6 @@ S: Maintained
|
|||
F: drivers/usb/gadget/udc/bcm63xx_udc.*
|
||||
|
||||
BROADCOM BCM7XXX ARM ARCHITECTURE
|
||||
M: Marc Carino <marc.ceeeee@gmail.com>
|
||||
M: Brian Norris <computersforpeace@gmail.com>
|
||||
M: Gregory Fong <gregory.0xf0@gmail.com>
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
|
@ -3912,7 +3927,7 @@ F: drivers/extcon/
|
|||
F: Documentation/extcon/
|
||||
|
||||
EXYNOS DP DRIVER
|
||||
M: Jingoo Han <jg1.han@samsung.com>
|
||||
M: Jingoo Han <jingoohan1@gmail.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/exynos/exynos_dp*
|
||||
|
|
@ -4371,11 +4386,10 @@ F: fs/gfs2/
|
|||
F: include/uapi/linux/gfs2_ondisk.h
|
||||
|
||||
GIGASET ISDN DRIVERS
|
||||
M: Hansjoerg Lipp <hjlipp@web.de>
|
||||
M: Tilman Schmidt <tilman@imap.cc>
|
||||
M: Paul Bolle <pebolle@tiscali.nl>
|
||||
L: gigaset307x-common@lists.sourceforge.net
|
||||
W: http://gigaset307x.sourceforge.net/
|
||||
S: Maintained
|
||||
S: Odd Fixes
|
||||
F: Documentation/isdn/README.gigaset
|
||||
F: drivers/isdn/gigaset/
|
||||
F: include/uapi/linux/gigaset_dev.h
|
||||
|
|
@ -4522,7 +4536,7 @@ M: Jean Delvare <jdelvare@suse.de>
|
|||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
W: http://www.lm-sensors.org/
|
||||
T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
|
||||
T: quilt http://jdelvare.nerim.net/devel/linux/jdelvare-hwmon/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
|
||||
S: Maintained
|
||||
F: Documentation/hwmon/
|
||||
|
|
@ -5042,17 +5056,19 @@ S: Orphan
|
|||
F: drivers/video/fbdev/imsttfb.c
|
||||
|
||||
INFINIBAND SUBSYSTEM
|
||||
M: Roland Dreier <roland@kernel.org>
|
||||
M: Doug Ledford <dledford@redhat.com>
|
||||
M: Sean Hefty <sean.hefty@intel.com>
|
||||
M: Hal Rosenstock <hal.rosenstock@gmail.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
W: http://www.openfabrics.org/
|
||||
Q: http://patchwork.kernel.org/project/linux-rdma/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma.git
|
||||
S: Supported
|
||||
F: Documentation/infiniband/
|
||||
F: drivers/infiniband/
|
||||
F: include/uapi/linux/if_infiniband.h
|
||||
F: include/uapi/rdma/
|
||||
F: include/rdma/
|
||||
|
||||
INOTIFY
|
||||
M: John McCutchan <john@johnmccutchan.com>
|
||||
|
|
@ -5805,6 +5821,7 @@ F: drivers/scsi/53c700*
|
|||
LED SUBSYSTEM
|
||||
M: Bryan Wu <cooloney@gmail.com>
|
||||
M: Richard Purdie <rpurdie@rpsys.net>
|
||||
M: Jacek Anaszewski <j.anaszewski@samsung.com>
|
||||
L: linux-leds@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds.git
|
||||
S: Maintained
|
||||
|
|
@ -6950,6 +6967,17 @@ T: git git://git.rocketboards.org/linux-socfpga-next.git
|
|||
S: Maintained
|
||||
F: arch/nios2/
|
||||
|
||||
NOKIA N900 POWER SUPPLY DRIVERS
|
||||
M: Pali Rohár <pali.rohar@gmail.com>
|
||||
S: Maintained
|
||||
F: include/linux/power/bq2415x_charger.h
|
||||
F: include/linux/power/bq27x00_battery.h
|
||||
F: include/linux/power/isp1704_charger.h
|
||||
F: drivers/power/bq2415x_charger.c
|
||||
F: drivers/power/bq27x00_battery.c
|
||||
F: drivers/power/isp1704_charger.c
|
||||
F: drivers/power/rx51_battery.c
|
||||
|
||||
NTB DRIVER
|
||||
M: Jon Mason <jdmason@kudzu.us>
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
|
|
@ -7538,7 +7566,7 @@ S: Maintained
|
|||
F: drivers/pci/host/*rcar*
|
||||
|
||||
PCI DRIVER FOR SAMSUNG EXYNOS
|
||||
M: Jingoo Han <jg1.han@samsung.com>
|
||||
M: Jingoo Han <jingoohan1@gmail.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
|
|
@ -7546,7 +7574,7 @@ S: Maintained
|
|||
F: drivers/pci/host/pci-exynos.c
|
||||
|
||||
PCI DRIVER FOR SYNOPSIS DESIGNWARE
|
||||
M: Jingoo Han <jg1.han@samsung.com>
|
||||
M: Jingoo Han <jingoohan1@gmail.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/pci/host/*designware*
|
||||
|
|
@ -8502,7 +8530,7 @@ S: Supported
|
|||
F: sound/soc/samsung/
|
||||
|
||||
SAMSUNG FRAMEBUFFER DRIVER
|
||||
M: Jingoo Han <jg1.han@samsung.com>
|
||||
M: Jingoo Han <jingoohan1@gmail.com>
|
||||
L: linux-fbdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/video/fbdev/s3c-fb.c
|
||||
|
|
@ -8807,10 +8835,11 @@ W: http://www.emulex.com
|
|||
S: Supported
|
||||
F: drivers/scsi/be2iscsi/
|
||||
|
||||
SERVER ENGINES 10Gbps NIC - BladeEngine 2 DRIVER
|
||||
M: Sathya Perla <sathya.perla@emulex.com>
|
||||
M: Subbu Seetharaman <subbu.seetharaman@emulex.com>
|
||||
M: Ajit Khaparde <ajit.khaparde@emulex.com>
|
||||
Emulex 10Gbps NIC BE2, BE3-R, Lancer, Skyhawk-R DRIVER
|
||||
M: Sathya Perla <sathya.perla@avagotech.com>
|
||||
M: Ajit Khaparde <ajit.khaparde@avagotech.com>
|
||||
M: Padmanabh Ratnakar <padmanabh.ratnakar@avagotech.com>
|
||||
M: Sriharsha Basavapatna <sriharsha.basavapatna@avagotech.com>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://www.emulex.com
|
||||
S: Supported
|
||||
|
|
@ -11037,6 +11066,7 @@ F: drivers/media/pci/zoran/
|
|||
ZRAM COMPRESSED RAM BLOCK DEVICE DRVIER
|
||||
M: Minchan Kim <minchan@kernel.org>
|
||||
M: Nitin Gupta <ngupta@vflare.org>
|
||||
R: Sergey Senozhatsky <sergey.senozhatsky.work@gmail.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/block/zram/
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 1
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc4
|
||||
NAME = Hurr durr I'ma sheep
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -2,19 +2,6 @@ menu "Kernel hacking"
|
|||
|
||||
source "lib/Kconfig.debug"
|
||||
|
||||
config EARLY_PRINTK
|
||||
bool "Early printk" if EMBEDDED
|
||||
default y
|
||||
help
|
||||
Write kernel log output directly into the VGA buffer or to a serial
|
||||
port.
|
||||
|
||||
This is useful for kernel debugging when your machine crashes very
|
||||
early before the console code is initialized. For normal operation
|
||||
it is not recommended because it looks ugly and doesn't cooperate
|
||||
with klogd/syslogd or the X server. You should normally N here,
|
||||
unless you want to debug such a crash.
|
||||
|
||||
config 16KSTACKS
|
||||
bool "Use 16Kb for kernel stacks instead of 8Kb"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ static inline void atomic_##op(int i, atomic_t *v) \
|
|||
atomic_ops_unlock(flags); \
|
||||
}
|
||||
|
||||
#define ATOMIC_OP_RETURN(op, c_op) \
|
||||
#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
|
||||
static inline int atomic_##op##_return(int i, atomic_t *v) \
|
||||
{ \
|
||||
unsigned long flags; \
|
||||
|
|
|
|||
|
|
@ -266,7 +266,7 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
|
|||
* Machine specific helpers for Entire D-Cache or Per Line ops
|
||||
*/
|
||||
|
||||
static unsigned int __before_dc_op(const int op)
|
||||
static inline unsigned int __before_dc_op(const int op)
|
||||
{
|
||||
unsigned int reg = reg;
|
||||
|
||||
|
|
@ -284,7 +284,7 @@ static unsigned int __before_dc_op(const int op)
|
|||
return reg;
|
||||
}
|
||||
|
||||
static void __after_dc_op(const int op, unsigned int reg)
|
||||
static inline void __after_dc_op(const int op, unsigned int reg)
|
||||
{
|
||||
if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
|
||||
while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ matrix_keypad: matrix_keypad@0 {
|
|||
pinctrl-0 = <&matrix_keypad_pins>;
|
||||
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <1500>;
|
||||
col-scan-delay-us = <5>;
|
||||
|
||||
row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
|
||||
&gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
|
||||
|
|
@ -473,7 +473,7 @@ edt-ft5306@38 {
|
|||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <31 0>;
|
||||
|
||||
wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
|
||||
|
||||
touchscreen-size-x = <480>;
|
||||
touchscreen-size-y = <272>;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = &mcp_rtc;
|
||||
rtc1 = &tps659038_rtc;
|
||||
rtc2 = &rtc;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
@ -83,7 +84,7 @@ led@3 {
|
|||
gpio_fan: gpio_fan {
|
||||
/* Based on 5v 500mA AFB02505HHB */
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = <0 0>,
|
||||
<13000 1>;
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -130,8 +131,8 @@ i2c3_pins_default: i2c3_pins_default {
|
|||
|
||||
uart3_pins_default: uart3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
|
||||
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
|
||||
0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
|
||||
0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -455,7 +456,7 @@ &i2c3 {
|
|||
mcp_rtc: rtc@6f {
|
||||
compatible = "microchip,mcp7941x";
|
||||
reg = <0x6f>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcp79410_pins_default>;
|
||||
|
|
@ -478,7 +479,7 @@ &cpu0 {
|
|||
&uart3 {
|
||||
status = "okay";
|
||||
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&dra7_pmx_core 0x248>;
|
||||
<&dra7_pmx_core 0x3f8>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins_default>;
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ clocks {
|
|||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
|
|
|
|||
|
|
@ -585,7 +585,7 @@ clocks {
|
|||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
/* 25 MHz reference crystal */
|
||||
|
|
|
|||
|
|
@ -502,7 +502,7 @@ clocks {
|
|||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -105,6 +105,10 @@ pcie@1,0 {
|
|||
};
|
||||
|
||||
internal-regs {
|
||||
rtc@10300 {
|
||||
/* No crystal connected to the internal RTC */
|
||||
status = "disabled";
|
||||
};
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -87,6 +87,7 @@ si5351: clock-generator {
|
|||
|
||||
/* connect xtal input to 25MHz reference */
|
||||
clocks = <&ref25>;
|
||||
clock-names = "xtal";
|
||||
|
||||
/* connect xtal input as source of pll0 and pll1 */
|
||||
silabs,pll-source = <0 0>, <1 0>;
|
||||
|
|
|
|||
|
|
@ -911,7 +911,7 @@ abb_mpu: regulator-abb-mpu {
|
|||
ti,clock-cycles = <16>;
|
||||
|
||||
reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
|
||||
<0x4ae06014 0x4>, <0x4a003b20 0x8>,
|
||||
<0x4ae06014 0x4>, <0x4a003b20 0xc>,
|
||||
<0x4ae0c158 0x4>;
|
||||
reg-names = "setup-address", "control-address",
|
||||
"int-address", "efuse-address",
|
||||
|
|
@ -944,7 +944,7 @@ abb_ivahd: regulator-abb-ivahd {
|
|||
ti,clock-cycles = <16>;
|
||||
|
||||
reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
|
||||
<0x4ae06010 0x4>, <0x4a0025cc 0x8>,
|
||||
<0x4ae06010 0x4>, <0x4a0025cc 0xc>,
|
||||
<0x4a002470 0x4>;
|
||||
reg-names = "setup-address", "control-address",
|
||||
"int-address", "efuse-address",
|
||||
|
|
@ -977,7 +977,7 @@ abb_dspeve: regulator-abb-dspeve {
|
|||
ti,clock-cycles = <16>;
|
||||
|
||||
reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
|
||||
<0x4ae06010 0x4>, <0x4a0025e0 0x8>,
|
||||
<0x4ae06010 0x4>, <0x4a0025e0 0xc>,
|
||||
<0x4a00246c 0x4>;
|
||||
reg-names = "setup-address", "control-address",
|
||||
"int-address", "efuse-address",
|
||||
|
|
@ -1010,7 +1010,7 @@ abb_gpu: regulator-abb-gpu {
|
|||
ti,clock-cycles = <16>;
|
||||
|
||||
reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
|
||||
<0x4ae06010 0x4>, <0x4a003b08 0x8>,
|
||||
<0x4ae06010 0x4>, <0x4a003b08 0xc>,
|
||||
<0x4ae0c154 0x4>;
|
||||
reg-names = "setup-address", "control-address",
|
||||
"int-address", "efuse-address",
|
||||
|
|
@ -1203,7 +1203,7 @@ omap_control_pcie2phy: control-pcie@0x4a003c44 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@48838000 {
|
||||
rtc: rtc@48838000 {
|
||||
compatible = "ti,am3352-rtc";
|
||||
reg = <0x48838000 0x100>;
|
||||
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include <dt-bindings/sound/samsung-i2s.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/clock/maxim,max77686.h>
|
||||
#include "exynos4412.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -105,6 +106,8 @@ watchdog@10060000 {
|
|||
|
||||
rtc@10070000 {
|
||||
status = "okay";
|
||||
clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
|
||||
clock-names = "rtc", "rtc_src";
|
||||
};
|
||||
|
||||
g2d@10800000 {
|
||||
|
|
|
|||
|
|
@ -567,6 +567,7 @@ &mmc_3 {
|
|||
num-slots = <1>;
|
||||
broken-cd;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
card-detect-delay = <200>;
|
||||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <2 3>;
|
||||
|
|
|
|||
|
|
@ -711,6 +711,7 @@ &mmc_1 {
|
|||
num-slots = <1>;
|
||||
broken-cd;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
card-detect-delay = <200>;
|
||||
clock-frequency = <400000000>;
|
||||
samsung,dw-mshc-ciu-div = <1>;
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ cpu-alert-2 {
|
|||
type = "active";
|
||||
};
|
||||
cpu-crit-0 {
|
||||
temperature = <1200000>; /* millicelsius */
|
||||
temperature = <120000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -536,6 +536,7 @@ dp: dp-controller@145B0000 {
|
|||
clock-names = "dp";
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
power-domains = <&disp_pd>;
|
||||
};
|
||||
|
||||
mipi_phy: video-phy@10040714 {
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ cpu-alert-0 {
|
|||
type = "active";
|
||||
};
|
||||
cpu-crit-0 {
|
||||
temperature = <1050000>; /* millicelsius */
|
||||
temperature = <105000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -674,6 +674,7 @@ &mmc_1 {
|
|||
num-slots = <1>;
|
||||
broken-cd;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
card-detect-delay = <200>;
|
||||
clock-frequency = <400000000>;
|
||||
samsung,dw-mshc-ciu-div = <1>;
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "imx23.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -93,6 +94,7 @@ usbphy0: usbphy@8007c000 {
|
|||
|
||||
ahb@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
dr_mode = "host";
|
||||
vbus-supply = <®_usb0_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -122,7 +124,7 @@ leds {
|
|||
|
||||
user {
|
||||
label = "green";
|
||||
gpios = <&gpio2 1 1>;
|
||||
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -428,6 +428,7 @@ slcdc@53fc0000 {
|
|||
|
||||
pwm4: pwm@53fc8000 {
|
||||
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
||||
#pwm-cells = <2>;
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
clocks = <&clks 108>, <&clks 52>;
|
||||
clock-names = "ipg", "per";
|
||||
|
|
|
|||
|
|
@ -913,7 +913,7 @@ dma_apbx: dma-apbx@80024000 {
|
|||
80 81 68 69
|
||||
70 71 72 73
|
||||
74 75 76 77>;
|
||||
interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
|
||||
interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
|
||||
"saif0", "saif1", "i2c0", "i2c1",
|
||||
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
|
||||
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ reg_usb_otg_vbus: regulator@0 {
|
|||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 15 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator@1 {
|
||||
|
|
@ -40,6 +41,7 @@ reg_usb_h1_vbus: regulator@1 {
|
|||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 0 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -185,7 +185,6 @@ vgen6_reg: vgen6 {
|
|||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
max7310_a: gpio@30 {
|
||||
|
|
|
|||
|
|
@ -498,6 +498,8 @@ tlv320aic3x: tlv320aic3x@18 {
|
|||
DRVDD-supply = <&vmmc2>;
|
||||
IOVDD-supply = <&vio>;
|
||||
DVDD-supply = <&vio>;
|
||||
|
||||
ai3x-micbias-vg = <1>;
|
||||
};
|
||||
|
||||
tlv320aic3x_aux: tlv320aic3x@19 {
|
||||
|
|
@ -509,6 +511,8 @@ tlv320aic3x_aux: tlv320aic3x@19 {
|
|||
DRVDD-supply = <&vmmc2>;
|
||||
IOVDD-supply = <&vio>;
|
||||
DVDD-supply = <&vio>;
|
||||
|
||||
ai3x-micbias-vg = <2>;
|
||||
};
|
||||
|
||||
tsl2563: tsl2563@29 {
|
||||
|
|
|
|||
|
|
@ -456,6 +456,7 @@ mmc3: mmc@480ad000 {
|
|||
};
|
||||
|
||||
mmu_isp: mmu@480bd400 {
|
||||
#iommu-cells = <0>;
|
||||
compatible = "ti,omap2-iommu";
|
||||
reg = <0x480bd400 0x80>;
|
||||
interrupts = <24>;
|
||||
|
|
@ -464,6 +465,7 @@ mmu_isp: mmu@480bd400 {
|
|||
};
|
||||
|
||||
mmu_iva: mmu@5d000000 {
|
||||
#iommu-cells = <0>;
|
||||
compatible = "ti,omap2-iommu";
|
||||
reg = <0x5d000000 0x80>;
|
||||
interrupts = <28>;
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ mpu {
|
|||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "ti,omap4-l3-noc", "simple-bus";
|
||||
compatible = "ti,omap5-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
|
|
|||
|
|
@ -545,7 +545,7 @@ hdmi@39 {
|
|||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
|
|
|
|||
|
|
@ -1017,23 +1017,6 @@ cpufreq-cooling {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
vmmci: regulator-gpio {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-name = "mmci-reg";
|
||||
regulator-type = "voltage";
|
||||
|
||||
startup-delay-us = <100>;
|
||||
enable-active-high;
|
||||
|
||||
states = <1800000 0x1
|
||||
2900000 0x0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcde@a0350000 {
|
||||
compatible = "stericsson,mcde";
|
||||
reg = <0xa0350000 0x1000>, /* MCDE */
|
||||
|
|
|
|||
|
|
@ -111,6 +111,21 @@ i2c@80110000 {
|
|||
pinctrl-1 = <&i2c3_sleep_mode>;
|
||||
};
|
||||
|
||||
vmmci: regulator-gpio {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-name = "mmci-reg";
|
||||
regulator-type = "voltage";
|
||||
|
||||
startup-delay-us = <100>;
|
||||
enable-active-high;
|
||||
|
||||
states = <1800000 0x1
|
||||
2900000 0x0>;
|
||||
};
|
||||
|
||||
// External Micro SD slot
|
||||
sdi0_per1@80126000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
|
|
|
|||
|
|
@ -146,8 +146,21 @@ ethernet@0 {
|
|||
};
|
||||
|
||||
vmmci: regulator-gpio {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
gpios = <&gpio7 4 0x4>;
|
||||
enable-gpio = <&gpio6 25 0x4>;
|
||||
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-name = "mmci-reg";
|
||||
regulator-type = "voltage";
|
||||
|
||||
startup-delay-us = <100>;
|
||||
enable-active-high;
|
||||
|
||||
states = <1800000 0x1
|
||||
2900000 0x0>;
|
||||
};
|
||||
|
||||
// External Micro SD slot
|
||||
|
|
|
|||
|
|
@ -826,7 +826,7 @@ phy1: usb-phy@0,7d000000 {
|
|||
<&tegra_car TEGRA124_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA124_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 59>, <&tegra_car 22>;
|
||||
resets = <&tegra_car 22>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
|
|
@ -838,6 +838,7 @@ phy1: usb-phy@0,7d000000 {
|
|||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
nvidia,has-utmi-pad-registers;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -862,7 +863,7 @@ phy2: usb-phy@0,7d004000 {
|
|||
<&tegra_car TEGRA124_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA124_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 22>, <&tegra_car 22>;
|
||||
resets = <&tegra_car 58>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
|
|
@ -874,7 +875,6 @@ phy2: usb-phy@0,7d004000 {
|
|||
nvidia,hssquelch-level = <2>;
|
||||
nvidia,hsdiscon-level = <5>;
|
||||
nvidia,xcvr-hsslew = <12>;
|
||||
nvidia,has-utmi-pad-registers;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -899,7 +899,7 @@ phy3: usb-phy@0,7d008000 {
|
|||
<&tegra_car TEGRA124_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA124_CLK_USBD>;
|
||||
clock-names = "reg", "pll_u", "utmi-pads";
|
||||
resets = <&tegra_car 58>, <&tegra_car 22>;
|
||||
resets = <&tegra_car 59>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
nvidia,hssync-start-delay = <0>;
|
||||
nvidia,idle-wait-delay = <17>;
|
||||
|
|
|
|||
|
|
@ -191,6 +191,7 @@ pmu {
|
|||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupts = <0 68 4>,
|
||||
<0 69 4>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
oscclk6a: oscclk6a {
|
||||
|
|
|
|||
|
|
@ -33,28 +33,28 @@ cpus {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
A9_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
A9_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
A9_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
A9_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
|
|
@ -170,6 +170,7 @@ L2: cache-controller@1e00a000 {
|
|||
compatible = "arm,pl310-cache";
|
||||
reg = <0x1e00a000 0x1000>;
|
||||
interrupts = <0 43 4>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
|
|
@ -181,6 +182,8 @@ pmu {
|
|||
<0 61 4>,
|
||||
<0 62 4>,
|
||||
<0 63 4>;
|
||||
interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
|
||||
|
||||
};
|
||||
|
||||
dcc {
|
||||
|
|
|
|||
|
|
@ -193,7 +193,7 @@ spi1: spi@e0007000 {
|
|||
};
|
||||
|
||||
gem0: ethernet@e000b000 {
|
||||
compatible = "cdns,gem";
|
||||
compatible = "cdns,zynq-gem";
|
||||
reg = <0xe000b000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupts = <0 22 4>;
|
||||
|
|
@ -204,7 +204,7 @@ gem0: ethernet@e000b000 {
|
|||
};
|
||||
|
||||
gem1: ethernet@e000c000 {
|
||||
compatible = "cdns,gem";
|
||||
compatible = "cdns,zynq-gem";
|
||||
reg = <0xe000c000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupts = <0 45 4>;
|
||||
|
|
|
|||
|
|
@ -39,11 +39,14 @@ CONFIG_ARCH_HIP04=y
|
|||
CONFIG_ARCH_KEYSTONE=y
|
||||
CONFIG_ARCH_MESON=y
|
||||
CONFIG_ARCH_MXC=y
|
||||
CONFIG_SOC_IMX50=y
|
||||
CONFIG_SOC_IMX51=y
|
||||
CONFIG_SOC_IMX53=y
|
||||
CONFIG_SOC_IMX6Q=y
|
||||
CONFIG_SOC_IMX6SL=y
|
||||
CONFIG_SOC_IMX6SX=y
|
||||
CONFIG_SOC_VF610=y
|
||||
CONFIG_SOC_LS1021A=y
|
||||
CONFIG_ARCH_OMAP3=y
|
||||
CONFIG_ARCH_OMAP4=y
|
||||
CONFIG_SOC_OMAP5=y
|
||||
|
|
|
|||
|
|
@ -393,7 +393,7 @@ CONFIG_TI_EDMA=y
|
|||
CONFIG_DMA_OMAP=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXTCON=m
|
||||
CONFIG_EXTCON_GPIO=m
|
||||
CONFIG_EXTCON_USB_GPIO=m
|
||||
CONFIG_EXTCON_PALMAS=m
|
||||
CONFIG_TI_EMIF=m
|
||||
CONFIG_PWM=y
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ struct dma_iommu_mapping {
|
|||
};
|
||||
|
||||
struct dma_iommu_mapping *
|
||||
arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size);
|
||||
arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size);
|
||||
|
||||
void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping);
|
||||
|
||||
|
|
|
|||
|
|
@ -110,5 +110,6 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
|
|||
bool xen_arch_need_swiotlb(struct device *dev,
|
||||
unsigned long pfn,
|
||||
unsigned long mfn);
|
||||
unsigned long xen_get_swiotlb_free_pages(unsigned int order);
|
||||
|
||||
#endif /* _ASM_ARM_XEN_PAGE_H */
|
||||
|
|
|
|||
|
|
@ -303,12 +303,17 @@ static int probe_current_pmu(struct arm_pmu *pmu)
|
|||
|
||||
static int of_pmu_irq_cfg(struct platform_device *pdev)
|
||||
{
|
||||
int i;
|
||||
int i, irq;
|
||||
int *irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
|
||||
|
||||
if (!irqs)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Don't bother with PPIs; they're already affine */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq >= 0 && irq_is_percpu(irq))
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < pdev->num_resources; ++i) {
|
||||
struct device_node *dn;
|
||||
int cpu;
|
||||
|
|
@ -317,7 +322,7 @@ static int of_pmu_irq_cfg(struct platform_device *pdev)
|
|||
i);
|
||||
if (!dn) {
|
||||
pr_warn("Failed to parse %s/interrupt-affinity[%d]\n",
|
||||
of_node_full_name(dn), i);
|
||||
of_node_full_name(pdev->dev.of_node), i);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -159,6 +159,8 @@ extern void exynos_enter_aftr(void);
|
|||
|
||||
extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
|
||||
|
||||
extern void exynos_set_delayed_reset_assertion(bool enable);
|
||||
|
||||
extern void s5p_init_cpu(void __iomem *cpuid_addr);
|
||||
extern unsigned int samsung_rev(void);
|
||||
extern void __iomem *cpu_boot_reg_base(void);
|
||||
|
|
|
|||
|
|
@ -166,6 +166,33 @@ static void __init exynos_init_io(void)
|
|||
exynos_map_io();
|
||||
}
|
||||
|
||||
/*
|
||||
* Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code
|
||||
* and suspend.
|
||||
*
|
||||
* This is necessary only on Exynos4 SoCs. When system is running
|
||||
* USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down
|
||||
* feature could properly detect global idle state when secondary CPU is
|
||||
* powered down.
|
||||
*
|
||||
* However this should not be set when such system is going into suspend.
|
||||
*/
|
||||
void exynos_set_delayed_reset_assertion(bool enable)
|
||||
{
|
||||
if (of_machine_is_compatible("samsung,exynos4")) {
|
||||
unsigned int tmp, core_id;
|
||||
|
||||
for (core_id = 0; core_id < num_possible_cpus(); core_id++) {
|
||||
tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
|
||||
if (enable)
|
||||
tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
|
||||
else
|
||||
tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
|
||||
pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Apparently, these SoCs are not able to wake-up from suspend using
|
||||
* the PMU. Too bad. Should they suddenly become capable of such a
|
||||
|
|
|
|||
|
|
@ -34,30 +34,6 @@
|
|||
|
||||
extern void exynos4_secondary_startup(void);
|
||||
|
||||
/*
|
||||
* Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs
|
||||
* during hot-(un)plugging CPUx.
|
||||
*
|
||||
* The feature can be cleared safely during first boot of secondary CPU.
|
||||
*
|
||||
* Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering
|
||||
* down a CPU so the CPU idle clock down feature could properly detect global
|
||||
* idle state when CPUx is off.
|
||||
*/
|
||||
static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)
|
||||
{
|
||||
if (soc_is_exynos4()) {
|
||||
unsigned int tmp;
|
||||
|
||||
tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
|
||||
if (enable)
|
||||
tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
|
||||
else
|
||||
tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
|
||||
pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static inline void cpu_leave_lowpower(u32 core_id)
|
||||
{
|
||||
|
|
@ -73,8 +49,6 @@ static inline void cpu_leave_lowpower(u32 core_id)
|
|||
: "=&r" (v)
|
||||
: "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
|
||||
exynos_set_delayed_reset_assertion(core_id, false);
|
||||
}
|
||||
|
||||
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
|
||||
|
|
@ -87,14 +61,6 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
|
|||
/* Turn the CPU off on next WFI instruction. */
|
||||
exynos_cpu_power_down(core_id);
|
||||
|
||||
/*
|
||||
* Exynos4 SoCs require setting
|
||||
* USE_DELAYED_RESET_ASSERTION so the CPU idle
|
||||
* clock down feature could properly detect
|
||||
* global idle state when CPUx is off.
|
||||
*/
|
||||
exynos_set_delayed_reset_assertion(core_id, true);
|
||||
|
||||
wfi();
|
||||
|
||||
if (pen_release == core_id) {
|
||||
|
|
@ -371,9 +337,6 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
udelay(10);
|
||||
}
|
||||
|
||||
/* No harm if this is called during first boot of secondary CPU */
|
||||
exynos_set_delayed_reset_assertion(core_id, false);
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
|
|
@ -420,6 +383,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
|
|||
|
||||
exynos_sysram_init();
|
||||
|
||||
exynos_set_delayed_reset_assertion(true);
|
||||
|
||||
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
|
||||
scu_enable(scu_base_addr());
|
||||
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@ static __init int exynos4_pm_init_power_domain(void)
|
|||
args.np = np;
|
||||
args.args_count = 0;
|
||||
child_domain = of_genpd_get_from_provider(&args);
|
||||
if (!child_domain)
|
||||
if (IS_ERR(child_domain))
|
||||
continue;
|
||||
|
||||
if (of_parse_phandle_with_args(np, "power-domains",
|
||||
|
|
@ -196,7 +196,7 @@ static __init int exynos4_pm_init_power_domain(void)
|
|||
continue;
|
||||
|
||||
parent_domain = of_genpd_get_from_provider(&args);
|
||||
if (!parent_domain)
|
||||
if (IS_ERR(parent_domain))
|
||||
continue;
|
||||
|
||||
if (pm_genpd_add_subdomain(parent_domain, child_domain))
|
||||
|
|
|
|||
|
|
@ -342,6 +342,8 @@ static void exynos_pm_enter_sleep_mode(void)
|
|||
|
||||
static void exynos_pm_prepare(void)
|
||||
{
|
||||
exynos_set_delayed_reset_assertion(false);
|
||||
|
||||
/* Set wake-up mask registers */
|
||||
exynos_pm_set_wakeup_mask();
|
||||
|
||||
|
|
@ -482,6 +484,7 @@ static void exynos_pm_resume(void)
|
|||
|
||||
/* Clear SLEEP mode set in INFORM1 */
|
||||
pmu_raw_writel(0x0, S5P_INFORM1);
|
||||
exynos_set_delayed_reset_assertion(true);
|
||||
}
|
||||
|
||||
static void exynos3250_pm_resume(void)
|
||||
|
|
@ -723,8 +726,10 @@ void __init exynos_pm_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL)))
|
||||
if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
|
||||
pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pm_data = (const struct exynos_pm_data *) match->data;
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
#ifndef __GEMINI_COMMON_H__
|
||||
#define __GEMINI_COMMON_H__
|
||||
|
||||
#include <linux/reboot.h>
|
||||
|
||||
struct mtd_partition;
|
||||
|
||||
extern void gemini_map_io(void);
|
||||
|
|
@ -26,6 +28,6 @@ extern int platform_register_pflash(unsigned int size,
|
|||
struct mtd_partition *parts,
|
||||
unsigned int nr_parts);
|
||||
|
||||
extern void gemini_restart(char mode, const char *cmd);
|
||||
extern void gemini_restart(enum reboot_mode mode, const char *cmd);
|
||||
|
||||
#endif /* __GEMINI_COMMON_H__ */
|
||||
|
|
|
|||
|
|
@ -14,7 +14,9 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/global_reg.h>
|
||||
|
||||
void gemini_restart(char mode, const char *cmd)
|
||||
#include "common.h"
|
||||
|
||||
void gemini_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
__raw_writel(RESET_GLOBAL | RESET_CPU1,
|
||||
IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
|
||||
* Copyright (C) 2010 Pengutronix, Wolfram Sang <kernel@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
|
|
|
|||
|
|
@ -171,6 +171,12 @@
|
|||
*/
|
||||
#define LINKS_PER_OCP_IF 2
|
||||
|
||||
/*
|
||||
* Address offset (in bytes) between the reset control and the reset
|
||||
* status registers: 4 bytes on OMAP4
|
||||
*/
|
||||
#define OMAP4_RST_CTRL_ST_OFFSET 4
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
|
||||
* @enable_module: function to enable a module (via MODULEMODE)
|
||||
|
|
@ -3016,10 +3022,12 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
|
|||
if (ohri->st_shift)
|
||||
pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
|
||||
oh->name, ohri->name);
|
||||
return omap_prm_deassert_hardreset(ohri->rst_shift, 0,
|
||||
return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
|
||||
oh->clkdm->pwrdm.ptr->prcm_partition,
|
||||
oh->clkdm->pwrdm.ptr->prcm_offs,
|
||||
oh->prcm.omap4.rstctrl_offs, 0);
|
||||
oh->prcm.omap4.rstctrl_offs,
|
||||
oh->prcm.omap4.rstctrl_offs +
|
||||
OMAP4_RST_CTRL_ST_OFFSET);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -3047,27 +3055,6 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
|
|||
oh->prcm.omap4.rstctrl_offs);
|
||||
}
|
||||
|
||||
/**
|
||||
* _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args
|
||||
* @oh: struct omap_hwmod * to assert hardreset
|
||||
* @ohri: hardreset line data
|
||||
*
|
||||
* Call am33xx_prminst_assert_hardreset() with parameters extracted
|
||||
* from the hwmod @oh and the hardreset line data @ohri. Only
|
||||
* intended for use as an soc_ops function pointer. Passes along the
|
||||
* return value from am33xx_prminst_assert_hardreset(). XXX This
|
||||
* function is scheduled for removal when the PRM code is moved into
|
||||
* drivers/.
|
||||
*/
|
||||
static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
|
||||
struct omap_hwmod_rst_info *ohri)
|
||||
|
||||
{
|
||||
return omap_prm_assert_hardreset(ohri->rst_shift, 0,
|
||||
oh->clkdm->pwrdm.ptr->prcm_offs,
|
||||
oh->prcm.omap4.rstctrl_offs);
|
||||
}
|
||||
|
||||
/**
|
||||
* _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
|
||||
* @oh: struct omap_hwmod * to deassert hardreset
|
||||
|
|
@ -3083,32 +3070,13 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
|
|||
static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
|
||||
struct omap_hwmod_rst_info *ohri)
|
||||
{
|
||||
return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
|
||||
return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift,
|
||||
oh->clkdm->pwrdm.ptr->prcm_partition,
|
||||
oh->clkdm->pwrdm.ptr->prcm_offs,
|
||||
oh->prcm.omap4.rstctrl_offs,
|
||||
oh->prcm.omap4.rstst_offs);
|
||||
}
|
||||
|
||||
/**
|
||||
* _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args
|
||||
* @oh: struct omap_hwmod * to test hardreset
|
||||
* @ohri: hardreset line data
|
||||
*
|
||||
* Call am33xx_prminst_is_hardreset_asserted() with parameters
|
||||
* extracted from the hwmod @oh and the hardreset line data @ohri.
|
||||
* Only intended for use as an soc_ops function pointer. Passes along
|
||||
* the return value from am33xx_prminst_is_hardreset_asserted(). XXX
|
||||
* This function is scheduled for removal when the PRM code is moved
|
||||
* into drivers/.
|
||||
*/
|
||||
static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
|
||||
struct omap_hwmod_rst_info *ohri)
|
||||
{
|
||||
return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0,
|
||||
oh->clkdm->pwrdm.ptr->prcm_offs,
|
||||
oh->prcm.omap4.rstctrl_offs);
|
||||
}
|
||||
|
||||
/* Public functions */
|
||||
|
||||
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
|
||||
|
|
@ -3908,21 +3876,13 @@ void __init omap_hwmod_init(void)
|
|||
soc_ops.init_clkdm = _init_clkdm;
|
||||
soc_ops.update_context_lost = _omap4_update_context_lost;
|
||||
soc_ops.get_context_lost = _omap4_get_context_lost;
|
||||
} else if (soc_is_am43xx()) {
|
||||
} else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) {
|
||||
soc_ops.enable_module = _omap4_enable_module;
|
||||
soc_ops.disable_module = _omap4_disable_module;
|
||||
soc_ops.wait_target_ready = _omap4_wait_target_ready;
|
||||
soc_ops.assert_hardreset = _omap4_assert_hardreset;
|
||||
soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
|
||||
soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
|
||||
soc_ops.init_clkdm = _init_clkdm;
|
||||
} else if (cpu_is_ti816x() || soc_is_am33xx()) {
|
||||
soc_ops.enable_module = _omap4_enable_module;
|
||||
soc_ops.disable_module = _omap4_disable_module;
|
||||
soc_ops.wait_target_ready = _omap4_wait_target_ready;
|
||||
soc_ops.assert_hardreset = _am33xx_assert_hardreset;
|
||||
soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
|
||||
soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
|
||||
soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
|
||||
soc_ops.init_clkdm = _init_clkdm;
|
||||
} else {
|
||||
WARN(1, "omap_hwmod: unknown SoC type\n");
|
||||
|
|
|
|||
|
|
@ -544,6 +544,44 @@ static struct omap_hwmod am43xx_hdq1w_hwmod = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
|
||||
.rev_offs = 0x0,
|
||||
.sysc_offs = 0x104,
|
||||
.sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
|
||||
.sysc_fields = &omap_hwmod_sysc_type2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
|
||||
.name = "vpfe",
|
||||
.sysc = &am43xx_vpfe_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod am43xx_vpfe0_hwmod = {
|
||||
.name = "vpfe0",
|
||||
.class = &am43xx_vpfe_hwmod_class,
|
||||
.clkdm_name = "l3s_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
.clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod am43xx_vpfe1_hwmod = {
|
||||
.name = "vpfe1",
|
||||
.class = &am43xx_vpfe_hwmod_class,
|
||||
.clkdm_name = "l3s_clkdm",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
.clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* Interfaces */
|
||||
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
|
||||
.master = &am33xx_l3_main_hwmod,
|
||||
|
|
@ -825,6 +863,34 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
|
||||
.master = &am43xx_vpfe0_hwmod,
|
||||
.slave = &am33xx_l3_main_hwmod,
|
||||
.clk = "l3_gclk",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
|
||||
.master = &am43xx_vpfe1_hwmod,
|
||||
.slave = &am33xx_l3_main_hwmod,
|
||||
.clk = "l3_gclk",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
|
||||
.master = &am33xx_l4_ls_hwmod,
|
||||
.slave = &am43xx_vpfe0_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
|
||||
.master = &am33xx_l4_ls_hwmod,
|
||||
.slave = &am43xx_vpfe1_hwmod,
|
||||
.clk = "l4ls_gclk",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&am33xx_l4_wkup__synctimer,
|
||||
&am43xx_l4_ls__timer8,
|
||||
|
|
@ -925,6 +991,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
|||
&am43xx_l4_ls__dss_dispc,
|
||||
&am43xx_l4_ls__dss_rfbi,
|
||||
&am43xx_l4_ls__hdq1w,
|
||||
&am43xx_l3__vpfe0,
|
||||
&am43xx_l3__vpfe1,
|
||||
&am43xx_l4_ls__vpfe0,
|
||||
&am43xx_l4_ls__vpfe1,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -144,5 +144,6 @@
|
|||
#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
|
||||
#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
|
||||
#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0
|
||||
|
||||
#define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068
|
||||
#define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -112,6 +112,7 @@
|
|||
#define OMAP3430_VC_CMD_ONLP_SHIFT 16
|
||||
#define OMAP3430_VC_CMD_RET_SHIFT 8
|
||||
#define OMAP3430_VC_CMD_OFF_SHIFT 0
|
||||
#define OMAP3430_SREN_MASK (1 << 4)
|
||||
#define OMAP3430_HSEN_MASK (1 << 3)
|
||||
#define OMAP3430_MCODE_MASK (0x7 << 0)
|
||||
#define OMAP3430_VALID_MASK (1 << 24)
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
|
||||
#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
|
||||
#define OMAP4430_HSMCODE_MASK (0x7 << 0)
|
||||
#define OMAP4430_SRMODEEN_MASK (1 << 4)
|
||||
#define OMAP4430_HSMODEEN_MASK (1 << 3)
|
||||
#define OMAP4430_HSSCLL_SHIFT 24
|
||||
#define OMAP4430_ICEPICK_RST_SHIFT 9
|
||||
|
|
|
|||
|
|
@ -87,12 +87,6 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
|
|||
return v;
|
||||
}
|
||||
|
||||
/*
|
||||
* Address offset (in bytes) between the reset control and the reset
|
||||
* status registers: 4 bytes on OMAP4
|
||||
*/
|
||||
#define OMAP4_RST_CTRL_ST_OFFSET 4
|
||||
|
||||
/**
|
||||
* omap4_prminst_is_hardreset_asserted - read the HW reset line state of
|
||||
* submodules contained in the hwmod module
|
||||
|
|
@ -141,11 +135,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
|
|||
* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
|
||||
* wait
|
||||
* @shift: register bit shift corresponding to the reset line to deassert
|
||||
* @st_shift: status bit offset, not used for OMAP4+
|
||||
* @st_shift: status bit offset corresponding to the reset line
|
||||
* @part: PRM partition
|
||||
* @inst: PRM instance offset
|
||||
* @rstctrl_offs: reset register offset
|
||||
* @st_offs: reset status register offset, not used for OMAP4+
|
||||
* @rstst_offs: reset status register offset
|
||||
*
|
||||
* Some IPs like dsp, ipu or iva contain processors that require an HW
|
||||
* reset line to be asserted / deasserted in order to fully enable the
|
||||
|
|
@ -157,11 +151,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
|
|||
* of reset, or -EBUSY if the submodule did not exit reset promptly.
|
||||
*/
|
||||
int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
|
||||
u16 rstctrl_offs, u16 st_offs)
|
||||
u16 rstctrl_offs, u16 rstst_offs)
|
||||
{
|
||||
int c;
|
||||
u32 mask = 1 << shift;
|
||||
u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
|
||||
u32 st_mask = 1 << st_shift;
|
||||
|
||||
/* Check the current status to avoid de-asserting the line twice */
|
||||
if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
|
||||
|
|
@ -169,13 +163,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
|
|||
return -EEXIST;
|
||||
|
||||
/* Clear the reset status by writing 1 to the status bit */
|
||||
omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
|
||||
omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
|
||||
rstst_offs);
|
||||
/* de-assert the reset control line */
|
||||
omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
|
||||
/* wait the status to be set */
|
||||
omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
|
||||
rstst_offs),
|
||||
omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
|
||||
inst, rstst_offs),
|
||||
MAX_MODULE_HARDRESET_WAIT, c);
|
||||
|
||||
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
|
||||
|
|
|
|||
|
|
@ -298,14 +298,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
|
|||
if (IS_ERR(src))
|
||||
return PTR_ERR(src);
|
||||
|
||||
if (clk_get_parent(timer->fclk) != src) {
|
||||
r = clk_set_parent(timer->fclk, src);
|
||||
if (r < 0) {
|
||||
pr_warn("%s: %s cannot set source\n", __func__,
|
||||
oh->name);
|
||||
clk_put(src);
|
||||
return r;
|
||||
}
|
||||
r = clk_set_parent(timer->fclk, src);
|
||||
if (r < 0) {
|
||||
pr_warn("%s: %s cannot set source\n", __func__, oh->name);
|
||||
clk_put(src);
|
||||
return r;
|
||||
}
|
||||
|
||||
clk_put(src);
|
||||
|
|
|
|||
|
|
@ -316,7 +316,8 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
|
|||
* idle. And we can also scale voltages to zero for off-idle.
|
||||
* Note that no actual voltage scaling during off-idle will
|
||||
* happen unless the board specific twl4030 PMIC scripts are
|
||||
* loaded.
|
||||
* loaded. See also omap_vc_i2c_init for comments regarding
|
||||
* erratum i531.
|
||||
*/
|
||||
val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
|
||||
if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
|
||||
|
|
@ -704,9 +705,16 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
|
|||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
|
||||
* erratum i531 "Extra Power Consumed When Repeated Start Operation
|
||||
* Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
|
||||
* Otherwise I2C4 eventually leads into about 23mW extra power being
|
||||
* consumed even during off idle using VMODE.
|
||||
*/
|
||||
i2c_high_speed = voltdm->pmic->i2c_high_speed;
|
||||
if (i2c_high_speed)
|
||||
voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
|
||||
voltdm->rmw(vc->common->i2c_cfg_clear_mask,
|
||||
vc->common->i2c_cfg_hsen_mask,
|
||||
vc->common->i2c_cfg_reg);
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ struct voltagedomain;
|
|||
* @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
|
||||
* @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
|
||||
* @i2c_cfg_reg: I2C configuration register offset
|
||||
* @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
|
||||
* @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
|
||||
* @i2c_mcode_mask: MCODE field mask for I2C config register
|
||||
*
|
||||
|
|
@ -52,6 +53,7 @@ struct omap_vc_common {
|
|||
u8 cmd_ret_shift;
|
||||
u8 cmd_off_shift;
|
||||
u8 i2c_cfg_reg;
|
||||
u8 i2c_cfg_clear_mask;
|
||||
u8 i2c_cfg_hsen_mask;
|
||||
u8 i2c_mcode_mask;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ static struct omap_vc_common omap3_vc_common = {
|
|||
.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
|
||||
.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
|
||||
.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
|
||||
.i2c_cfg_clear_mask = OMAP3430_SREN_MASK | OMAP3430_HSEN_MASK,
|
||||
.i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
|
||||
.i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET,
|
||||
.i2c_mcode_mask = OMAP3430_MCODE_MASK,
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ static const struct omap_vc_common omap4_vc_common = {
|
|||
.cmd_ret_shift = OMAP4430_RET_SHIFT,
|
||||
.cmd_off_shift = OMAP4430_OFF_SHIFT,
|
||||
.i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
|
||||
.i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK,
|
||||
.i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
|
||||
.i2c_mcode_mask = OMAP4430_HSMCODE_MASK,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -691,4 +691,13 @@ config SHARPSL_PM_MAX1111
|
|||
config PXA310_ULPI
|
||||
bool
|
||||
|
||||
config PXA_SYSTEMS_CPLDS
|
||||
tristate "Motherboard cplds"
|
||||
default ARCH_LUBBOCK || MACH_MAINSTONE
|
||||
help
|
||||
This driver supports the Lubbock and Mainstone multifunction chip
|
||||
found on the pxa25x development platform system (Lubbock) and pxa27x
|
||||
development platform system (Mainstone). This IO board supports the
|
||||
interrupts handling, ethernet controller, flash chips, etc ...
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -90,4 +90,5 @@ obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o
|
|||
obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o
|
||||
obj-$(CONFIG_MACH_ZIPIT2) += z2.o
|
||||
|
||||
obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o
|
||||
obj-$(CONFIG_TOSA_BT) += tosa-bt.o
|
||||
|
|
|
|||
|
|
@ -37,7 +37,9 @@
|
|||
#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
|
||||
|
||||
/* Board specific IRQs */
|
||||
#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x))
|
||||
#define LUBBOCK_NR_IRQS IRQ_BOARD_START
|
||||
|
||||
#define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x))
|
||||
#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
|
||||
#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
|
||||
#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
|
||||
|
|
@ -47,8 +49,7 @@
|
|||
#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
|
||||
#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
|
||||
|
||||
#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16)
|
||||
#define LUBBOCK_NR_IRQS (IRQ_BOARD_START + 16 + 55)
|
||||
#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
|
||||
|
|
|
|||
|
|
@ -120,7 +120,9 @@
|
|||
#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */
|
||||
|
||||
/* board specific IRQs */
|
||||
#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
|
||||
#define MAINSTONE_NR_IRQS IRQ_BOARD_START
|
||||
|
||||
#define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x))
|
||||
#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
|
||||
#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
|
||||
#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
|
||||
|
|
@ -136,6 +138,4 @@
|
|||
#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
|
||||
#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
|
||||
|
||||
#define MAINSTONE_NR_IRQS (IRQ_BOARD_START + 16)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio/machine.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
|
@ -123,84 +124,6 @@ void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
|
|||
}
|
||||
EXPORT_SYMBOL(lubbock_set_misc_wr);
|
||||
|
||||
static unsigned long lubbock_irq_enabled;
|
||||
|
||||
static void lubbock_mask_irq(struct irq_data *d)
|
||||
{
|
||||
int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
|
||||
LUB_IRQ_MASK_EN = (lubbock_irq_enabled &= ~(1 << lubbock_irq));
|
||||
}
|
||||
|
||||
static void lubbock_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
|
||||
/* the irq can be acknowledged only if deasserted, so it's done here */
|
||||
LUB_IRQ_SET_CLR &= ~(1 << lubbock_irq);
|
||||
LUB_IRQ_MASK_EN = (lubbock_irq_enabled |= (1 << lubbock_irq));
|
||||
}
|
||||
|
||||
static struct irq_chip lubbock_irq_chip = {
|
||||
.name = "FPGA",
|
||||
.irq_ack = lubbock_mask_irq,
|
||||
.irq_mask = lubbock_mask_irq,
|
||||
.irq_unmask = lubbock_unmask_irq,
|
||||
};
|
||||
|
||||
static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
|
||||
do {
|
||||
/* clear our parent irq */
|
||||
desc->irq_data.chip->irq_ack(&desc->irq_data);
|
||||
if (likely(pending)) {
|
||||
irq = LUBBOCK_IRQ(0) + __ffs(pending);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
|
||||
} while (pending);
|
||||
}
|
||||
|
||||
static void __init lubbock_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
pxa25x_init_irq();
|
||||
|
||||
/* setup extra lubbock irqs */
|
||||
for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
|
||||
irq_set_chip_and_handler(irq, &lubbock_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lubbock_irq_handler);
|
||||
irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static void lubbock_irq_resume(void)
|
||||
{
|
||||
LUB_IRQ_MASK_EN = lubbock_irq_enabled;
|
||||
}
|
||||
|
||||
static struct syscore_ops lubbock_irq_syscore_ops = {
|
||||
.resume = lubbock_irq_resume,
|
||||
};
|
||||
|
||||
static int __init lubbock_irq_device_init(void)
|
||||
{
|
||||
if (machine_is_lubbock()) {
|
||||
register_syscore_ops(&lubbock_irq_syscore_ops);
|
||||
return 0;
|
||||
}
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
device_initcall(lubbock_irq_device_init);
|
||||
|
||||
#endif
|
||||
|
||||
static int lubbock_udc_is_connected(void)
|
||||
{
|
||||
return (LUB_MISC_RD & (1 << 9)) == 0;
|
||||
|
|
@ -383,11 +306,38 @@ static struct platform_device lubbock_flash_device[2] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct resource lubbock_cplds_resources[] = {
|
||||
[0] = {
|
||||
.start = LUBBOCK_FPGA_PHYS + 0xc0,
|
||||
.end = LUBBOCK_FPGA_PHYS + 0xe0 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = PXA_GPIO_TO_IRQ(0),
|
||||
.end = PXA_GPIO_TO_IRQ(0),
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
|
||||
},
|
||||
[2] = {
|
||||
.start = LUBBOCK_IRQ(0),
|
||||
.end = LUBBOCK_IRQ(6),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device lubbock_cplds_device = {
|
||||
.name = "pxa_cplds_irqs",
|
||||
.id = -1,
|
||||
.resource = &lubbock_cplds_resources[0],
|
||||
.num_resources = 3,
|
||||
};
|
||||
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&sa1111_device,
|
||||
&smc91x_device,
|
||||
&lubbock_flash_device[0],
|
||||
&lubbock_flash_device[1],
|
||||
&lubbock_cplds_device,
|
||||
};
|
||||
|
||||
static struct pxafb_mode_info sharp_lm8v31_mode = {
|
||||
|
|
@ -648,7 +598,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
|
|||
/* Maintainer: MontaVista Software Inc. */
|
||||
.map_io = lubbock_map_io,
|
||||
.nr_irqs = LUBBOCK_NR_IRQS,
|
||||
.init_irq = lubbock_init_irq,
|
||||
.init_irq = pxa25x_init_irq,
|
||||
.handle_irq = pxa25x_handle_irq,
|
||||
.init_time = pxa_timer_init,
|
||||
.init_machine = lubbock_init,
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio/machine.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
|
@ -122,92 +123,6 @@ static unsigned long mainstone_pin_config[] = {
|
|||
GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
|
||||
};
|
||||
|
||||
static unsigned long mainstone_irq_enabled;
|
||||
|
||||
static void mainstone_mask_irq(struct irq_data *d)
|
||||
{
|
||||
int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
|
||||
MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
|
||||
}
|
||||
|
||||
static void mainstone_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
|
||||
/* the irq can be acknowledged only if deasserted, so it's done here */
|
||||
MST_INTSETCLR &= ~(1 << mainstone_irq);
|
||||
MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
|
||||
}
|
||||
|
||||
static struct irq_chip mainstone_irq_chip = {
|
||||
.name = "FPGA",
|
||||
.irq_ack = mainstone_mask_irq,
|
||||
.irq_mask = mainstone_mask_irq,
|
||||
.irq_unmask = mainstone_unmask_irq,
|
||||
};
|
||||
|
||||
static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
|
||||
do {
|
||||
/* clear useless edge notification */
|
||||
desc->irq_data.chip->irq_ack(&desc->irq_data);
|
||||
if (likely(pending)) {
|
||||
irq = MAINSTONE_IRQ(0) + __ffs(pending);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
pending = MST_INTSETCLR & mainstone_irq_enabled;
|
||||
} while (pending);
|
||||
}
|
||||
|
||||
static void __init mainstone_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
pxa27x_init_irq();
|
||||
|
||||
/* setup extra Mainstone irqs */
|
||||
for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
|
||||
irq_set_chip_and_handler(irq, &mainstone_irq_chip,
|
||||
handle_level_irq);
|
||||
if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
|
||||
else
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
set_irq_flags(MAINSTONE_IRQ(8), 0);
|
||||
set_irq_flags(MAINSTONE_IRQ(12), 0);
|
||||
|
||||
MST_INTMSKENA = 0;
|
||||
MST_INTSETCLR = 0;
|
||||
|
||||
irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), mainstone_irq_handler);
|
||||
irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static void mainstone_irq_resume(void)
|
||||
{
|
||||
MST_INTMSKENA = mainstone_irq_enabled;
|
||||
}
|
||||
|
||||
static struct syscore_ops mainstone_irq_syscore_ops = {
|
||||
.resume = mainstone_irq_resume,
|
||||
};
|
||||
|
||||
static int __init mainstone_irq_device_init(void)
|
||||
{
|
||||
if (machine_is_mainstone())
|
||||
register_syscore_ops(&mainstone_irq_syscore_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(mainstone_irq_device_init);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = (MST_ETH_PHYS + 0x300),
|
||||
|
|
@ -487,11 +402,37 @@ static struct platform_device mst_gpio_keys_device = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct resource mst_cplds_resources[] = {
|
||||
[0] = {
|
||||
.start = MST_FPGA_PHYS + 0xc0,
|
||||
.end = MST_FPGA_PHYS + 0xe0 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = PXA_GPIO_TO_IRQ(0),
|
||||
.end = PXA_GPIO_TO_IRQ(0),
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
|
||||
},
|
||||
[2] = {
|
||||
.start = MAINSTONE_IRQ(0),
|
||||
.end = MAINSTONE_IRQ(15),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device mst_cplds_device = {
|
||||
.name = "pxa_cplds_irqs",
|
||||
.id = -1,
|
||||
.resource = &mst_cplds_resources[0],
|
||||
.num_resources = 3,
|
||||
};
|
||||
|
||||
static struct platform_device *platform_devices[] __initdata = {
|
||||
&smc91x_device,
|
||||
&mst_flash_device[0],
|
||||
&mst_flash_device[1],
|
||||
&mst_gpio_keys_device,
|
||||
&mst_cplds_device,
|
||||
};
|
||||
|
||||
static struct pxaohci_platform_data mainstone_ohci_platform_data = {
|
||||
|
|
@ -718,7 +659,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
|
|||
.atag_offset = 0x100, /* BLOB boot parameter setting */
|
||||
.map_io = mainstone_map_io,
|
||||
.nr_irqs = MAINSTONE_NR_IRQS,
|
||||
.init_irq = mainstone_init_irq,
|
||||
.init_irq = pxa27x_init_irq,
|
||||
.handle_irq = pxa27x_handle_irq,
|
||||
.init_time = pxa_timer_init,
|
||||
.init_machine = mainstone_init,
|
||||
|
|
|
|||
200
arch/arm/mach-pxa/pxa_cplds_irqs.c
Normal file
200
arch/arm/mach-pxa/pxa_cplds_irqs.c
Normal file
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* Intel Reference Systems cplds
|
||||
*
|
||||
* Copyright (C) 2014 Robert Jarzmik
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* Cplds motherboard driver, supporting lubbock and mainstone SoC board.
|
||||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/mfd/core.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#define FPGA_IRQ_MASK_EN 0x0
|
||||
#define FPGA_IRQ_SET_CLR 0x10
|
||||
|
||||
#define CPLDS_NB_IRQ 32
|
||||
|
||||
struct cplds {
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
unsigned int irq_mask;
|
||||
struct gpio_desc *gpio0;
|
||||
struct irq_domain *irqdomain;
|
||||
};
|
||||
|
||||
static irqreturn_t cplds_irq_handler(int in_irq, void *d)
|
||||
{
|
||||
struct cplds *fpga = d;
|
||||
unsigned long pending;
|
||||
unsigned int bit;
|
||||
|
||||
pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
|
||||
for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
|
||||
generic_handle_irq(irq_find_mapping(fpga->irqdomain, bit));
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void cplds_irq_mask_ack(struct irq_data *d)
|
||||
{
|
||||
struct cplds *fpga = irq_data_get_irq_chip_data(d);
|
||||
unsigned int cplds_irq = irqd_to_hwirq(d);
|
||||
unsigned int set, bit = BIT(cplds_irq);
|
||||
|
||||
fpga->irq_mask &= ~bit;
|
||||
writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
|
||||
set = readl(fpga->base + FPGA_IRQ_SET_CLR);
|
||||
writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR);
|
||||
}
|
||||
|
||||
static void cplds_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct cplds *fpga = irq_data_get_irq_chip_data(d);
|
||||
unsigned int cplds_irq = irqd_to_hwirq(d);
|
||||
unsigned int bit = BIT(cplds_irq);
|
||||
|
||||
fpga->irq_mask |= bit;
|
||||
writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
|
||||
}
|
||||
|
||||
static struct irq_chip cplds_irq_chip = {
|
||||
.name = "pxa_cplds",
|
||||
.irq_mask_ack = cplds_irq_mask_ack,
|
||||
.irq_unmask = cplds_irq_unmask,
|
||||
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
|
||||
};
|
||||
|
||||
static int cplds_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
struct cplds *fpga = d->host_data;
|
||||
|
||||
irq_set_chip_and_handler(irq, &cplds_irq_chip, handle_level_irq);
|
||||
irq_set_chip_data(irq, fpga);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops cplds_irq_domain_ops = {
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
.map = cplds_irq_domain_map,
|
||||
};
|
||||
|
||||
static int cplds_resume(struct platform_device *pdev)
|
||||
{
|
||||
struct cplds *fpga = platform_get_drvdata(pdev);
|
||||
|
||||
writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cplds_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct cplds *fpga;
|
||||
int ret;
|
||||
unsigned int base_irq = 0;
|
||||
unsigned long irqflags = 0;
|
||||
|
||||
fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL);
|
||||
if (!fpga)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (res) {
|
||||
fpga->irq = (unsigned int)res->start;
|
||||
irqflags = res->flags;
|
||||
}
|
||||
if (!fpga->irq)
|
||||
return -ENODEV;
|
||||
|
||||
base_irq = platform_get_irq(pdev, 1);
|
||||
if (base_irq < 0)
|
||||
base_irq = 0;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
fpga->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(fpga->base))
|
||||
return PTR_ERR(fpga->base);
|
||||
|
||||
platform_set_drvdata(pdev, fpga);
|
||||
|
||||
writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
|
||||
writel(0, fpga->base + FPGA_IRQ_SET_CLR);
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
|
||||
irqflags, dev_name(&pdev->dev), fpga);
|
||||
if (ret == -ENOSYS)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "couldn't request main irq%d: %d\n",
|
||||
fpga->irq, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
irq_set_irq_wake(fpga->irq, 1);
|
||||
fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
|
||||
CPLDS_NB_IRQ,
|
||||
&cplds_irq_domain_ops, fpga);
|
||||
if (!fpga->irqdomain)
|
||||
return -ENODEV;
|
||||
|
||||
if (base_irq) {
|
||||
ret = irq_create_strict_mappings(fpga->irqdomain, base_irq, 0,
|
||||
CPLDS_NB_IRQ);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "couldn't create the irq mapping %d..%d\n",
|
||||
base_irq, base_irq + CPLDS_NB_IRQ);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cplds_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct cplds *fpga = platform_get_drvdata(pdev);
|
||||
|
||||
irq_set_chip_and_handler(fpga->irq, NULL, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id cplds_id_table[] = {
|
||||
{ .compatible = "intel,lubbock-cplds-irqs", },
|
||||
{ .compatible = "intel,mainstone-cplds-irqs", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, cplds_id_table);
|
||||
|
||||
static struct platform_driver cplds_driver = {
|
||||
.driver = {
|
||||
.name = "pxa_cplds_irqs",
|
||||
.of_match_table = of_match_ptr(cplds_id_table),
|
||||
},
|
||||
.probe = cplds_probe,
|
||||
.remove = cplds_remove,
|
||||
.resume = cplds_resume,
|
||||
};
|
||||
|
||||
module_platform_driver(cplds_driver);
|
||||
|
||||
MODULE_DESCRIPTION("PXA Cplds interrupts driver");
|
||||
MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -83,6 +83,13 @@ static void rk3288_slp_mode_set(int level)
|
|||
SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
|
||||
| SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
|
||||
|
||||
/*
|
||||
* The dapswjdp can not auto reset before resume, that cause it may
|
||||
* access some illegal address during resume. Let's disable it before
|
||||
* suspend, and the MASKROM will enable it back.
|
||||
*/
|
||||
regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
|
||||
|
||||
/* booting address of resuming system is from this register value */
|
||||
regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
|
||||
rk3288_bootram_phy);
|
||||
|
|
|
|||
|
|
@ -55,6 +55,10 @@ static inline void rockchip_suspend_init(void)
|
|||
#define SGRF_FAST_BOOT_EN BIT(8)
|
||||
#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
|
||||
|
||||
#define RK3288_SGRF_CPU_CON0 (0x40)
|
||||
#define SGRF_DAPDEVICEEN BIT(0)
|
||||
#define SGRF_DAPDEVICEEN_WRITE BIT(16)
|
||||
|
||||
#define RK3288_CRU_MODE_CON 0x50
|
||||
#define RK3288_CRU_SEL0_CON 0x60
|
||||
#define RK3288_CRU_SEL1_CON 0x64
|
||||
|
|
|
|||
|
|
@ -30,11 +30,30 @@
|
|||
#include "pm.h"
|
||||
|
||||
#define RK3288_GRF_SOC_CON0 0x244
|
||||
#define RK3288_TIMER6_7_PHYS 0xff810000
|
||||
|
||||
static void __init rockchip_timer_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("rockchip,rk3288")) {
|
||||
struct regmap *grf;
|
||||
void __iomem *reg_base;
|
||||
|
||||
/*
|
||||
* Most/all uboot versions for rk3288 don't enable timer7
|
||||
* which is needed for the architected timer to work.
|
||||
* So make sure it is running during early boot.
|
||||
*/
|
||||
reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
|
||||
if (reg_base) {
|
||||
writel(0, reg_base + 0x30);
|
||||
writel(0xffffffff, reg_base + 0x20);
|
||||
writel(0xffffffff, reg_base + 0x24);
|
||||
writel(1, reg_base + 0x30);
|
||||
dsb();
|
||||
iounmap(reg_base);
|
||||
} else {
|
||||
pr_err("rockchip: could not map timer7 registers\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable auto jtag/sdmmc switching that causes issues
|
||||
|
|
|
|||
|
|
@ -1878,7 +1878,7 @@ struct dma_map_ops iommu_coherent_ops = {
|
|||
* arm_iommu_attach_device function.
|
||||
*/
|
||||
struct dma_iommu_mapping *
|
||||
arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
|
||||
arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
|
||||
{
|
||||
unsigned int bits = size >> PAGE_SHIFT;
|
||||
unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
|
||||
|
|
@ -1886,6 +1886,10 @@ arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
|
|||
int extensions = 1;
|
||||
int err = -ENOMEM;
|
||||
|
||||
/* currently only 32-bit DMA address space is supported */
|
||||
if (size > DMA_BIT_MASK(32) + 1)
|
||||
return ERR_PTR(-ERANGE);
|
||||
|
||||
if (!bitmap_size)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
|
|
@ -2057,13 +2061,6 @@ static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
|
|||
if (!iommu)
|
||||
return false;
|
||||
|
||||
/*
|
||||
* currently arm_iommu_create_mapping() takes a max of size_t
|
||||
* for size param. So check this limit for now.
|
||||
*/
|
||||
if (size > SIZE_MAX)
|
||||
return false;
|
||||
|
||||
mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
|
||||
if (IS_ERR(mapping)) {
|
||||
pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
|
||||
|
|
|
|||
|
|
@ -22,8 +22,6 @@
|
|||
*
|
||||
* These are the low level assembler for performing cache and TLB
|
||||
* functions on the arm1020.
|
||||
*
|
||||
* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
|
|
|||
|
|
@ -22,8 +22,6 @@
|
|||
*
|
||||
* These are the low level assembler for performing cache and TLB
|
||||
* functions on the arm1020e.
|
||||
*
|
||||
* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
|
|
|||
|
|
@ -441,9 +441,6 @@ ENTRY(cpu_arm925_set_pte_ext)
|
|||
.type __arm925_setup, #function
|
||||
__arm925_setup:
|
||||
mov r0, #0
|
||||
#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
|
||||
orr r0,r0,#1 << 7
|
||||
#endif
|
||||
|
||||
/* Transparent on, D-cache clean & flush mode. See NOTE2 above */
|
||||
orr r0,r0,#1 << 1 @ transparent mode on
|
||||
|
|
|
|||
|
|
@ -602,7 +602,6 @@ __\name\()_proc_info:
|
|||
PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ
|
||||
initfn __feroceon_setup, __\name\()_proc_info
|
||||
.long __feroceon_setup
|
||||
.long cpu_arch_name
|
||||
.long cpu_elf_name
|
||||
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@
|
|||
#define SEEN_DATA (1 << (BPF_MEMWORDS + 3))
|
||||
|
||||
#define FLAG_NEED_X_RESET (1 << 0)
|
||||
#define FLAG_IMM_OVERFLOW (1 << 1)
|
||||
|
||||
struct jit_ctx {
|
||||
const struct bpf_prog *skf;
|
||||
|
|
@ -293,6 +294,15 @@ static u16 imm_offset(u32 k, struct jit_ctx *ctx)
|
|||
/* PC in ARM mode == address of the instruction + 8 */
|
||||
imm = offset - (8 + ctx->idx * 4);
|
||||
|
||||
if (imm & ~0xfff) {
|
||||
/*
|
||||
* literal pool is too far, signal it into flags. we
|
||||
* can only detect it on the second pass unfortunately.
|
||||
*/
|
||||
ctx->flags |= FLAG_IMM_OVERFLOW;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return imm;
|
||||
}
|
||||
|
||||
|
|
@ -449,10 +459,21 @@ static inline void emit_udiv(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx)
|
|||
return;
|
||||
}
|
||||
#endif
|
||||
if (rm != ARM_R0)
|
||||
emit(ARM_MOV_R(ARM_R0, rm), ctx);
|
||||
|
||||
/*
|
||||
* For BPF_ALU | BPF_DIV | BPF_K instructions, rm is ARM_R4
|
||||
* (r_A) and rn is ARM_R0 (r_scratch) so load rn first into
|
||||
* ARM_R1 to avoid accidentally overwriting ARM_R0 with rm
|
||||
* before using it as a source for ARM_R1.
|
||||
*
|
||||
* For BPF_ALU | BPF_DIV | BPF_X rm is ARM_R4 (r_A) and rn is
|
||||
* ARM_R5 (r_X) so there is no particular register overlap
|
||||
* issues.
|
||||
*/
|
||||
if (rn != ARM_R1)
|
||||
emit(ARM_MOV_R(ARM_R1, rn), ctx);
|
||||
if (rm != ARM_R0)
|
||||
emit(ARM_MOV_R(ARM_R0, rm), ctx);
|
||||
|
||||
ctx->seen |= SEEN_CALL;
|
||||
emit_mov_i(ARM_R3, (u32)jit_udiv, ctx);
|
||||
|
|
@ -855,6 +876,14 @@ static int build_body(struct jit_ctx *ctx)
|
|||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (ctx->flags & FLAG_IMM_OVERFLOW)
|
||||
/*
|
||||
* this instruction generated an overflow when
|
||||
* trying to access the literal pool, so
|
||||
* delegate this filter to the kernel interpreter.
|
||||
*/
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* compute offsets only during the first pass */
|
||||
|
|
@ -917,7 +946,14 @@ void bpf_jit_compile(struct bpf_prog *fp)
|
|||
ctx.idx = 0;
|
||||
|
||||
build_prologue(&ctx);
|
||||
build_body(&ctx);
|
||||
if (build_body(&ctx) < 0) {
|
||||
#if __LINUX_ARM_ARCH__ < 7
|
||||
if (ctx.imm_count)
|
||||
kfree(ctx.imms);
|
||||
#endif
|
||||
bpf_jit_binary_free(header);
|
||||
goto out;
|
||||
}
|
||||
build_epilogue(&ctx);
|
||||
|
||||
flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx));
|
||||
|
|
|
|||
|
|
@ -272,6 +272,7 @@ void xen_arch_pre_suspend(void) { }
|
|||
void xen_arch_post_suspend(int suspend_cancelled) { }
|
||||
void xen_timer_resume(void) { }
|
||||
void xen_arch_resume(void) { }
|
||||
void xen_arch_suspend(void) { }
|
||||
|
||||
|
||||
/* In the hypervisor.S file. */
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#include <linux/gfp.h>
|
||||
#include <linux/highmem.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
|
|
@ -21,6 +22,20 @@
|
|||
#include <asm/xen/hypercall.h>
|
||||
#include <asm/xen/interface.h>
|
||||
|
||||
unsigned long xen_get_swiotlb_free_pages(unsigned int order)
|
||||
{
|
||||
struct memblock_region *reg;
|
||||
gfp_t flags = __GFP_NOWARN;
|
||||
|
||||
for_each_memblock(memory, reg) {
|
||||
if (reg->base < (phys_addr_t)0xffffffff) {
|
||||
flags |= __GFP_DMA;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return __get_free_pages(flags, order);
|
||||
}
|
||||
|
||||
enum dma_cache_op {
|
||||
DMA_UNMAP,
|
||||
DMA_MAP,
|
||||
|
|
|
|||
|
|
@ -21,6 +21,20 @@ mb_clk25mhz: clk25mhz {
|
|||
clock-output-names = "juno_mb:clk25mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "juno_mb:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "juno_mb:refclk32khz";
|
||||
};
|
||||
|
||||
motherboard {
|
||||
compatible = "arm,vexpress,v2p-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
|
|
@ -66,6 +80,15 @@ iofpga@3,00000000 {
|
|||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
|
||||
v2m_sysctl: sysctl@020000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x020000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
};
|
||||
|
||||
mmci@050000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
|
|
@ -106,16 +129,16 @@ v2m_timer01: timer@110000 {
|
|||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x110000 0x10000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "timclken1", "apb_pclk";
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@120000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x120000 0x10000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "timclken1", "apb_pclk";
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@170000 {
|
||||
|
|
|
|||
|
|
@ -147,13 +147,21 @@ static int chksum_final(struct shash_desc *desc, u8 *out)
|
|||
{
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
put_unaligned_le32(ctx->crc, out);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chksumc_final(struct shash_desc *desc, u8 *out)
|
||||
{
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
put_unaligned_le32(~ctx->crc, out);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __chksum_finup(u32 crc, const u8 *data, unsigned int len, u8 *out)
|
||||
{
|
||||
put_unaligned_le32(~crc32_arm64_le_hw(crc, data, len), out);
|
||||
put_unaligned_le32(crc32_arm64_le_hw(crc, data, len), out);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -199,6 +207,14 @@ static int crc32_cra_init(struct crypto_tfm *tfm)
|
|||
{
|
||||
struct chksum_ctx *mctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
mctx->key = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int crc32c_cra_init(struct crypto_tfm *tfm)
|
||||
{
|
||||
struct chksum_ctx *mctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
mctx->key = ~0;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -229,7 +245,7 @@ static struct shash_alg crc32c_alg = {
|
|||
.setkey = chksum_setkey,
|
||||
.init = chksum_init,
|
||||
.update = chksumc_update,
|
||||
.final = chksum_final,
|
||||
.final = chksumc_final,
|
||||
.finup = chksumc_finup,
|
||||
.digest = chksumc_digest,
|
||||
.descsize = sizeof(struct chksum_desc_ctx),
|
||||
|
|
@ -241,7 +257,7 @@ static struct shash_alg crc32c_alg = {
|
|||
.cra_alignmask = 0,
|
||||
.cra_ctxsize = sizeof(struct chksum_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_init = crc32_cra_init,
|
||||
.cra_init = crc32c_cra_init,
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -74,6 +74,9 @@ static int sha1_ce_finup(struct shash_desc *desc, const u8 *data,
|
|||
|
||||
static int sha1_ce_final(struct shash_desc *desc, u8 *out)
|
||||
{
|
||||
struct sha1_ce_state *sctx = shash_desc_ctx(desc);
|
||||
|
||||
sctx->finalize = 0;
|
||||
kernel_neon_begin_partial(16);
|
||||
sha1_base_do_finalize(desc, (sha1_block_fn *)sha1_ce_transform);
|
||||
kernel_neon_end();
|
||||
|
|
|
|||
|
|
@ -75,6 +75,9 @@ static int sha256_ce_finup(struct shash_desc *desc, const u8 *data,
|
|||
|
||||
static int sha256_ce_final(struct shash_desc *desc, u8 *out)
|
||||
{
|
||||
struct sha256_ce_state *sctx = shash_desc_ctx(desc);
|
||||
|
||||
sctx->finalize = 0;
|
||||
kernel_neon_begin_partial(28);
|
||||
sha256_base_do_finalize(desc, (sha256_block_fn *)sha2_ce_transform);
|
||||
kernel_neon_end();
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/alternative.h>
|
||||
#include <asm/cpufeature.h>
|
||||
#include <asm/insn.h>
|
||||
#include <linux/stop_machine.h>
|
||||
|
||||
extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
|
||||
|
|
@ -34,48 +33,6 @@ struct alt_region {
|
|||
struct alt_instr *end;
|
||||
};
|
||||
|
||||
/*
|
||||
* Decode the imm field of a b/bl instruction, and return the byte
|
||||
* offset as a signed value (so it can be used when computing a new
|
||||
* branch target).
|
||||
*/
|
||||
static s32 get_branch_offset(u32 insn)
|
||||
{
|
||||
s32 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
|
||||
|
||||
/* sign-extend the immediate before turning it into a byte offset */
|
||||
return (imm << 6) >> 4;
|
||||
}
|
||||
|
||||
static u32 get_alt_insn(u8 *insnptr, u8 *altinsnptr)
|
||||
{
|
||||
u32 insn;
|
||||
|
||||
aarch64_insn_read(altinsnptr, &insn);
|
||||
|
||||
/* Stop the world on instructions we don't support... */
|
||||
BUG_ON(aarch64_insn_is_cbz(insn));
|
||||
BUG_ON(aarch64_insn_is_cbnz(insn));
|
||||
BUG_ON(aarch64_insn_is_bcond(insn));
|
||||
/* ... and there is probably more. */
|
||||
|
||||
if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
|
||||
enum aarch64_insn_branch_type type;
|
||||
unsigned long target;
|
||||
|
||||
if (aarch64_insn_is_b(insn))
|
||||
type = AARCH64_INSN_BRANCH_NOLINK;
|
||||
else
|
||||
type = AARCH64_INSN_BRANCH_LINK;
|
||||
|
||||
target = (unsigned long)altinsnptr + get_branch_offset(insn);
|
||||
insn = aarch64_insn_gen_branch_imm((unsigned long)insnptr,
|
||||
target, type);
|
||||
}
|
||||
|
||||
return insn;
|
||||
}
|
||||
|
||||
static int __apply_alternatives(void *alt_region)
|
||||
{
|
||||
struct alt_instr *alt;
|
||||
|
|
@ -83,9 +40,6 @@ static int __apply_alternatives(void *alt_region)
|
|||
u8 *origptr, *replptr;
|
||||
|
||||
for (alt = region->begin; alt < region->end; alt++) {
|
||||
u32 insn;
|
||||
int i;
|
||||
|
||||
if (!cpus_have_cap(alt->cpufeature))
|
||||
continue;
|
||||
|
||||
|
|
@ -95,12 +49,7 @@ static int __apply_alternatives(void *alt_region)
|
|||
|
||||
origptr = (u8 *)&alt->orig_offset + alt->orig_offset;
|
||||
replptr = (u8 *)&alt->alt_offset + alt->alt_offset;
|
||||
|
||||
for (i = 0; i < alt->alt_len; i += sizeof(insn)) {
|
||||
insn = get_alt_insn(origptr + i, replptr + i);
|
||||
aarch64_insn_write(origptr + i, insn);
|
||||
}
|
||||
|
||||
memcpy(origptr, replptr, alt->alt_len);
|
||||
flush_icache_range((uintptr_t)origptr,
|
||||
(uintptr_t)(origptr + alt->alt_len));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1315,15 +1315,15 @@ static int armpmu_device_probe(struct platform_device *pdev)
|
|||
if (!cpu_pmu)
|
||||
return -ENODEV;
|
||||
|
||||
irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
|
||||
if (!irqs)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Don't bother with PPIs; they're already affine */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq >= 0 && irq_is_percpu(irq))
|
||||
return 0;
|
||||
|
||||
irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
|
||||
if (!irqs)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < pdev->num_resources; ++i) {
|
||||
struct device_node *dn;
|
||||
int cpu;
|
||||
|
|
|
|||
|
|
@ -328,10 +328,12 @@ static int ptdump_init(void)
|
|||
for (j = 0; j < pg_level[i].num; j++)
|
||||
pg_level[i].mask |= pg_level[i].bits[j].mask;
|
||||
|
||||
#ifdef CONFIG_SPARSEMEM_VMEMMAP
|
||||
address_markers[VMEMMAP_START_NR].start_address =
|
||||
(unsigned long)virt_to_page(PAGE_OFFSET);
|
||||
address_markers[VMEMMAP_END_NR].start_address =
|
||||
(unsigned long)virt_to_page(high_memory);
|
||||
#endif
|
||||
|
||||
pe = debugfs_create_file("kernel_page_tables", 0400, NULL, NULL,
|
||||
&ptdump_fops);
|
||||
|
|
|
|||
|
|
@ -487,7 +487,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
imm64 = (u64)insn1.imm << 32 | imm;
|
||||
imm64 = (u64)insn1.imm << 32 | (u32)imm;
|
||||
emit_a64_mov_i64(dst, imm64, ctx);
|
||||
|
||||
return 1;
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ static volatile unsigned long flushcache_cpumask = 0;
|
|||
/*
|
||||
* For flush_tlb_others()
|
||||
*/
|
||||
static volatile cpumask_t flush_cpumask;
|
||||
static cpumask_t flush_cpumask;
|
||||
static struct mm_struct *flush_mm;
|
||||
static struct vm_area_struct *flush_vma;
|
||||
static volatile unsigned long flush_va;
|
||||
|
|
@ -415,7 +415,7 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
|
|||
*/
|
||||
send_IPI_mask(&cpumask, INVALIDATE_TLB_IPI, 0);
|
||||
|
||||
while (!cpumask_empty((cpumask_t*)&flush_cpumask)) {
|
||||
while (!cpumask_empty(&flush_cpumask)) {
|
||||
/* nothing. lockup detection does not belong here */
|
||||
mb();
|
||||
}
|
||||
|
|
@ -468,7 +468,7 @@ void smp_invalidate_interrupt(void)
|
|||
__flush_tlb_page(va);
|
||||
}
|
||||
}
|
||||
cpumask_clear_cpu(cpu_id, (cpumask_t*)&flush_cpumask);
|
||||
cpumask_clear_cpu(cpu_id, &flush_cpumask);
|
||||
}
|
||||
|
||||
/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user