forked from luck/tmp_suning_uos_patched
ASoC: Avoid direct register cache access when setting defaults
Directly accessing the register cache means that we can't use anything except a flat register cache so use snd_soc_update_bits(). Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
parent
203db22071
commit
a1b3b5eeee
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@ -414,7 +414,6 @@ static int wm8523_resume(struct snd_soc_codec *codec)
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static int wm8523_probe(struct snd_soc_codec *codec)
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{
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struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec);
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u16 *reg_cache = codec->reg_cache;
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int ret, i;
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codec->hw_write = (hw_write_t)i2c_master_send;
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@ -471,8 +470,9 @@ static int wm8523_probe(struct snd_soc_codec *codec)
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}
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/* Change some default settings - latch VU and enable ZC */
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reg_cache[WM8523_DAC_GAINR] |= WM8523_DACR_VU;
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reg_cache[WM8523_DAC_CTRL3] |= WM8523_ZC;
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snd_soc_update_bits(codec, WM8523_DAC_GAINR,
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WM8523_DACR_VU, WM8523_DACR_VU);
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snd_soc_update_bits(codec, WM8523_DAC_CTRL3, WM8523_ZC, WM8523_ZC);
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wm8523_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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@ -421,7 +421,6 @@ static int wm8741_resume(struct snd_soc_codec *codec)
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static int wm8741_probe(struct snd_soc_codec *codec)
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{
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struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);
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u16 *reg_cache = codec->reg_cache;
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int ret = 0;
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ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8741->control_type);
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@ -437,10 +436,14 @@ static int wm8741_probe(struct snd_soc_codec *codec)
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}
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/* Change some default settings - latch VU */
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reg_cache[WM8741_DACLLSB_ATTENUATION] |= WM8741_UPDATELL;
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reg_cache[WM8741_DACLMSB_ATTENUATION] |= WM8741_UPDATELM;
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reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERL;
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reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERM;
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snd_soc_update_bits(codec, WM8741_DACLLSB_ATTENUATION,
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WM8741_UPDATELL, WM8741_UPDATELL);
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snd_soc_update_bits(codec, WM8741_DACLMSB_ATTENUATION,
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WM8741_UPDATELM, WM8741_UPDATELM);
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snd_soc_update_bits(codec, WM8741_DACRLSB_ATTENUATION,
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WM8741_UPDATERL, WM8741_UPDATERL);
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snd_soc_update_bits(codec, WM8741_DACRLSB_ATTENUATION,
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WM8741_UPDATERM, WM8741_UPDATERM);
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snd_soc_add_controls(codec, wm8741_snd_controls,
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ARRAY_SIZE(wm8741_snd_controls));
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@ -2436,19 +2436,28 @@ static int wm8904_probe(struct snd_soc_codec *codec)
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}
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/* Change some default settings - latch VU and enable ZC */
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reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU;
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reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU;
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reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU;
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reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU;
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reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU |
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WM8904_HPOUTLZC;
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reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU |
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WM8904_HPOUTRZC;
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reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU |
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WM8904_LINEOUTLZC;
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reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU |
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WM8904_LINEOUTRZC;
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reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
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snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_LEFT,
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WM8904_ADC_VU, WM8904_ADC_VU);
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snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
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WM8904_ADC_VU, WM8904_ADC_VU);
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snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_LEFT,
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WM8904_DAC_VU, WM8904_DAC_VU);
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snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
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WM8904_DAC_VU, WM8904_DAC_VU);
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snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_LEFT,
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WM8904_HPOUT_VU | WM8904_HPOUTLZC,
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WM8904_HPOUT_VU | WM8904_HPOUTLZC);
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snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_RIGHT,
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WM8904_HPOUT_VU | WM8904_HPOUTRZC,
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WM8904_HPOUT_VU | WM8904_HPOUTRZC);
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snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_LEFT,
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WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
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WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
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snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_RIGHT,
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WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
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WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
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snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0,
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WM8904_SR_MODE, 0);
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/* Apply configuration from the platform data. */
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if (wm8904->pdata) {
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@ -2469,10 +2478,12 @@ static int wm8904_probe(struct snd_soc_codec *codec)
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/* Set Class W by default - this will be managed by the Class
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* G widget at runtime where bypass paths are available.
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*/
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reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR;
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snd_soc_update_bits(codec, WM8904_CLASS_W_0,
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WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
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/* Use normal bias source */
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reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL;
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snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
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WM8904_POBCTRL, 0);
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wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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@ -934,16 +934,27 @@ static int wm8955_probe(struct snd_soc_codec *codec)
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}
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/* Change some default settings - latch VU and enable ZC */
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reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
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reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
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reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
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reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
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reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
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reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
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reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
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snd_soc_update_bits(codec, WM8955_LEFT_DAC_VOLUME,
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WM8955_LDVU, WM8955_LDVU);
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snd_soc_update_bits(codec, WM8955_RIGHT_DAC_VOLUME,
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WM8955_RDVU, WM8955_RDVU);
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snd_soc_update_bits(codec, WM8955_LOUT1_VOLUME,
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WM8955_LO1VU | WM8955_LO1ZC,
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WM8955_LO1VU | WM8955_LO1ZC);
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snd_soc_update_bits(codec, WM8955_ROUT1_VOLUME,
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WM8955_RO1VU | WM8955_RO1ZC,
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WM8955_RO1VU | WM8955_RO1ZC);
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snd_soc_update_bits(codec, WM8955_LOUT2_VOLUME,
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WM8955_LO2VU | WM8955_LO2ZC,
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WM8955_LO2VU | WM8955_LO2ZC);
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snd_soc_update_bits(codec, WM8955_ROUT2_VOLUME,
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WM8955_RO2VU | WM8955_RO2ZC,
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WM8955_RO2VU | WM8955_RO2ZC);
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snd_soc_update_bits(codec, WM8955_MONOOUT_VOLUME,
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WM8955_MOZC, WM8955_MOZC);
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/* Also enable adaptive bass boost by default */
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reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
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snd_soc_update_bits(codec, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
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/* Set platform data values */
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if (pdata) {
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@ -3822,16 +3822,26 @@ static int wm8962_probe(struct snd_soc_codec *codec)
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}
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/* Latch volume update bits */
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reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
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reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
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reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
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reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
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reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
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reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
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reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
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reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
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reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
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reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
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snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
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WM8962_IN_VU, WM8962_IN_VU);
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snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
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WM8962_IN_VU, WM8962_IN_VU);
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snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
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WM8962_ADC_VU, WM8962_ADC_VU);
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snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
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WM8962_ADC_VU, WM8962_ADC_VU);
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snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
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WM8962_DAC_VU, WM8962_DAC_VU);
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snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
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WM8962_DAC_VU, WM8962_DAC_VU);
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snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
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WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
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snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
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WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
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snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
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WM8962_HPOUT_VU, WM8962_HPOUT_VU);
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snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
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WM8962_HPOUT_VU, WM8962_HPOUT_VU);
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wm8962_add_widgets(codec);
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@ -965,7 +965,7 @@ static int wm8978_probe(struct snd_soc_codec *codec)
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* written.
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*/
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for (i = 0; i < ARRAY_SIZE(update_reg); i++)
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((u16 *)codec->reg_cache)[update_reg[i]] |= 0x100;
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snd_soc_update_bits(codec, update_reg[i], 0x100, 0x100);
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/* Reset the codec */
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ret = snd_soc_write(codec, WM8978_RESET, 0);
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@ -551,7 +551,6 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec,
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static int wm9090_probe(struct snd_soc_codec *codec)
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{
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struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec);
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u16 *reg_cache = codec->reg_cache;
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int ret;
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codec->control_data = wm9090->control_data;
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@ -576,22 +575,30 @@ static int wm9090_probe(struct snd_soc_codec *codec)
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/* Configure some defaults; they will be written out when we
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* bring the bias up.
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*/
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reg_cache[WM9090_IN1_LINE_INPUT_A_VOLUME] |= WM9090_IN1_VU
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| WM9090_IN1A_ZC;
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reg_cache[WM9090_IN1_LINE_INPUT_B_VOLUME] |= WM9090_IN1_VU
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| WM9090_IN1B_ZC;
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reg_cache[WM9090_IN2_LINE_INPUT_A_VOLUME] |= WM9090_IN2_VU
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| WM9090_IN2A_ZC;
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reg_cache[WM9090_IN2_LINE_INPUT_B_VOLUME] |= WM9090_IN2_VU
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| WM9090_IN2B_ZC;
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reg_cache[WM9090_SPEAKER_VOLUME_LEFT] |=
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WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC;
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reg_cache[WM9090_LEFT_OUTPUT_VOLUME] |=
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WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC;
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reg_cache[WM9090_RIGHT_OUTPUT_VOLUME] |=
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WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC;
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snd_soc_update_bits(codec, WM9090_IN1_LINE_INPUT_A_VOLUME,
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WM9090_IN1_VU | WM9090_IN1A_ZC,
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WM9090_IN1_VU | WM9090_IN1A_ZC);
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snd_soc_update_bits(codec, WM9090_IN1_LINE_INPUT_B_VOLUME,
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WM9090_IN1_VU | WM9090_IN1B_ZC,
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WM9090_IN1_VU | WM9090_IN1B_ZC);
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snd_soc_update_bits(codec, WM9090_IN2_LINE_INPUT_A_VOLUME,
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WM9090_IN2_VU | WM9090_IN2A_ZC,
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WM9090_IN2_VU | WM9090_IN2A_ZC);
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snd_soc_update_bits(codec, WM9090_IN2_LINE_INPUT_B_VOLUME,
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WM9090_IN2_VU | WM9090_IN2B_ZC,
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WM9090_IN2_VU | WM9090_IN2B_ZC);
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snd_soc_update_bits(codec, WM9090_SPEAKER_VOLUME_LEFT,
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WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC,
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WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC);
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snd_soc_update_bits(codec, WM9090_LEFT_OUTPUT_VOLUME,
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WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC,
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WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC);
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snd_soc_update_bits(codec, WM9090_RIGHT_OUTPUT_VOLUME,
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WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC,
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WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC);
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reg_cache[WM9090_CLOCKING_1] |= WM9090_TOCLK_ENA;
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snd_soc_update_bits(codec, WM9090_CLOCKING_1,
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WM9090_TOCLK_ENA, WM9090_TOCLK_ENA);
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wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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