forked from luck/tmp_suning_uos_patched
Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: ARM: 7099/1: futex: preserve oldval in SMP __futex_atomic_op ARM: dma-mapping: free allocated page if unable to map ARM: fix vmlinux.lds.S discarding sections ARM: nommu: fix warning with checksyscalls.sh ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeed
This commit is contained in:
Linus Torvalds
commit
a2b49102da
@ -1283,6 +1283,20 @@ config ARM_ERRATA_364296
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processor into full low interrupt latency mode. ARM11MPCore
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is not affected.
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config ARM_ERRATA_764369
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bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
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depends on CPU_V7 && SMP
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help
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This option enables the workaround for erratum 764369
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affecting Cortex-A9 MPCore with two or more processors (all
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current revisions). Under certain timing circumstances, a data
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cache line maintenance operation by MVA targeting an Inner
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Shareable memory region may fail to proceed up to either the
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Point of Coherency or to the Point of Unification of the
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system. This workaround adds a DSB instruction before the
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relevant cache maintenance functions and sets a specific bit
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in the diagnostic control register of the SCU.
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endmenu
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source "arch/arm/common/Kconfig"
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@ -25,17 +25,17 @@
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#ifdef CONFIG_SMP
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
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smp_mb(); \
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__asm__ __volatile__( \
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"1: ldrex %1, [%2]\n" \
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"1: ldrex %1, [%3]\n" \
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" " insn "\n" \
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"2: strex %1, %0, [%2]\n" \
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" teq %1, #0\n" \
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"2: strex %2, %0, [%3]\n" \
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" teq %2, #0\n" \
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" bne 1b\n" \
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" mov %0, #0\n" \
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__futex_atomic_ex_table("%4") \
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: "=&r" (ret), "=&r" (oldval) \
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__futex_atomic_ex_table("%5") \
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: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
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: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
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: "cc", "memory")
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@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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#include <linux/preempt.h>
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#include <asm/domain.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
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__asm__ __volatile__( \
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"1: " T(ldr) " %1, [%2]\n" \
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"1: " T(ldr) " %1, [%3]\n" \
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" " insn "\n" \
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"2: " T(str) " %0, [%2]\n" \
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"2: " T(str) " %0, [%3]\n" \
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" mov %0, #0\n" \
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__futex_atomic_ex_table("%4") \
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: "=&r" (ret), "=&r" (oldval) \
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__futex_atomic_ex_table("%5") \
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: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
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: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
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: "cc", "memory")
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@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret;
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int oldval = 0, ret, tmp;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
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__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
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__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
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__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
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__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
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__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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@ -478,8 +478,8 @@
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/*
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* Unimplemented (or alternatively implemented) syscalls
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*/
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#define __IGNORE_fadvise64_64 1
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#define __IGNORE_migrate_pages 1
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#define __IGNORE_fadvise64_64
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#define __IGNORE_migrate_pages
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#endif /* __KERNEL__ */
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#endif /* __ASM_ARM_UNISTD_H */
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@ -13,6 +13,7 @@
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#include <asm/smp_scu.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#define SCU_CTRL 0x00
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#define SCU_CONFIG 0x04
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@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
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{
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u32 scu_ctrl;
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#ifdef CONFIG_ARM_ERRATA_764369
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/* Cortex-A9 only */
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if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
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scu_ctrl = __raw_readl(scu_base + 0x30);
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if (!(scu_ctrl & 1))
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__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
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}
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#endif
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scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
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/* already enabled? */
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if (scu_ctrl & 1)
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@ -23,8 +23,10 @@
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#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
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#define ARM_EXIT_KEEP(x) x
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#define ARM_EXIT_DISCARD(x)
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#else
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#define ARM_EXIT_KEEP(x)
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#define ARM_EXIT_DISCARD(x) x
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#endif
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OUTPUT_ARCH(arm)
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@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
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SECTIONS
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{
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/*
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* XXX: The linker does not define how output sections are
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* assigned to input sections when there are multiple statements
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* matching the same input section name. There is no documented
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* order of matching.
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*
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* unwind exit sections must be discarded before the rest of the
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* unwind sections get included.
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*/
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@ -47,6 +54,9 @@ SECTIONS
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*(.ARM.extab.exit.text)
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ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
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ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
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ARM_EXIT_DISCARD(EXIT_TEXT)
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ARM_EXIT_DISCARD(EXIT_DATA)
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EXIT_CALL
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#ifndef CONFIG_HOTPLUG
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*(.ARM.exidx.devexit.text)
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*(.ARM.extab.devexit.text)
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@ -58,6 +68,8 @@ SECTIONS
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#ifndef CONFIG_SMP_ON_UP
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*(.alt.smp.init)
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#endif
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*(.discard)
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*(.discard.*)
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}
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#ifdef CONFIG_XIP_KERNEL
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@ -279,9 +291,6 @@ SECTIONS
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STABS_DEBUG
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.comment 0 : { *(.comment) }
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/* Default discards */
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DISCARDS
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}
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/*
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@ -174,6 +174,10 @@ ENTRY(v7_coherent_user_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r12, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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1:
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USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
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add r12, r12, r2
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@ -223,6 +227,10 @@ ENTRY(v7_flush_kern_dcache_area)
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add r1, r0, r1
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sub r3, r2, #1
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bic r0, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
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add r0, r0, r2
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@ -247,6 +255,10 @@ v7_dma_inv_range:
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sub r3, r2, #1
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tst r0, r3
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bic r0, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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tst r1, r3
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@ -270,6 +282,10 @@ v7_dma_clean_range:
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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1:
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mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
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add r0, r0, r2
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@ -288,6 +304,10 @@ ENTRY(v7_dma_flush_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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#ifdef CONFIG_ARM_ERRATA_764369
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ALT_SMP(W(dsb))
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ALT_UP(W(nop))
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#endif
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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add r0, r0, r2
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@ -324,6 +324,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
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if (addr)
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*handle = pfn_to_dma(dev, page_to_pfn(page));
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else
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__dma_free_buffer(page, size);
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return addr;
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}
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