forked from luck/tmp_suning_uos_patched
[POWERPC] QE: get rid of most device_types and model
Now we're searching for "fsl,qe", "fsl,qe-muram", "fsl,qe-muram-data" and "fsl,qe-ic". Unfortunately it's still impossible to remove device_type = "qe" from the existing device trees because older u-boots are looking for it. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
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f67be814ff
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a2dd70a11d
@ -1543,7 +1543,7 @@ platforms are moved over to use the flattened-device-tree model.
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i) Root QE device
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Required properties:
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- device_type : should be "qe";
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- compatible : should be "fsl,qe";
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- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
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- reg : offset and length of the device registers.
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- bus-frequency : the clock frequency for QUICC Engine.
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@ -1557,8 +1557,7 @@ platforms are moved over to use the flattened-device-tree model.
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "qe";
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model = "QE";
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compatible = "fsl,qe";
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ranges = <0 e0100000 00100000>;
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reg = <e0100000 480>;
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brg-frequency = <0>;
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@ -1781,7 +1780,7 @@ platforms are moved over to use the flattened-device-tree model.
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vii) Multi-User RAM (MURAM)
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Required properties:
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- device_type : should be "muram".
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- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
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- mode : the could be "host" or "slave".
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- ranges : Should be defined as specified in 1) to describe the
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translation of MURAM addresses.
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@ -1791,10 +1790,12 @@ platforms are moved over to use the flattened-device-tree model.
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Example:
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muram@10000 {
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device_type = "muram";
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0 00010000 0000c000>;
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data-only@0{
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0 c000>;
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};
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};
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@ -206,17 +206,18 @@ qe@e0100000 {
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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model = "QE";
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ranges = <0 e0100000 00100000>;
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reg = <e0100000 480>;
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brg-frequency = <0>;
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bus-frequency = <BCD3D80>;
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muram@10000 {
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device_type = "muram";
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0 00010000 00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0 4000>;
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};
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};
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@ -320,9 +321,9 @@ phy4: ethernet-phy@04 {
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};
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};
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qeic: qeic@80 {
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qeic: interrupt-controller@80 {
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interrupt-controller;
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device_type = "qeic";
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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@ -166,17 +166,19 @@ qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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model = "QE";
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compatible = "fsl,qe";
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ranges = <0 e0100000 00100000>;
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reg = <e0100000 480>;
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brg-frequency = <0>;
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bus-frequency = <BCD3D80>;
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muram@10000 {
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device_type = "muram";
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0 00010000 00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0 4000>;
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};
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};
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@ -252,9 +254,9 @@ phy04:ethernet-phy@04 {
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};
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};
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qeic:qeic@80 {
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qeic:interrupt-controller@80 {
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interrupt-controller;
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device_type = "qeic";
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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@ -207,17 +207,19 @@ qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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model = "QE";
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compatible = "fsl,qe";
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ranges = <0 e0100000 00100000>;
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reg = <e0100000 480>;
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brg-frequency = <0>;
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bus-frequency = <179A7B00>;
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muram@10000 {
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device_type = "muram";
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0 00010000 0000c000>;
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data-only@0{
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0 c000>;
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};
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};
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@ -303,9 +305,9 @@ phy1: ethernet-phy@01 {
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};
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};
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qeic: qeic@80 {
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qeic: interrupt-controller@80 {
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interrupt-controller;
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device_type = "qeic";
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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@ -284,17 +284,19 @@ qe@e0080000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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model = "QE";
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compatible = "fsl,qe";
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ranges = <0 e0080000 00040000>;
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reg = <e0080000 480>;
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brg-frequency = <0>;
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bus-frequency = <179A7B00>;
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muram@10000 {
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device_type = "muram";
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0 00010000 0000c000>;
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data-only@0{
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0 c000>;
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};
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};
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@ -385,9 +387,9 @@ qe_phy3: ethernet-phy@03 {
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};
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};
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qeic: qeic@80 {
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qeic: interrupt-controller@80 {
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interrupt-controller;
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device_type = "qeic";
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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@ -105,6 +105,7 @@ static struct of_device_id mpc832x_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "qe", },
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{ .compatible = "fsl,qe", },
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{},
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};
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@ -134,10 +135,12 @@ static void __init mpc832x_sys_init_IRQ(void)
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of_node_put(np);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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@ -115,6 +115,7 @@ static struct of_device_id mpc832x_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "qe", },
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{ .compatible = "fsl,qe", },
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{},
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};
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@ -145,10 +146,12 @@ void __init mpc832x_rdb_init_IRQ(void)
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of_node_put(np);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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@ -136,6 +136,7 @@ static struct of_device_id mpc836x_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "qe", },
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{ .compatible = "fsl,qe", },
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{},
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};
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@ -165,10 +166,12 @@ static void __init mpc836x_mds_init_IRQ(void)
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of_node_put(np);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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@ -94,21 +94,25 @@ static void __init mpc85xx_mds_setup_arch(void)
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#endif
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#ifdef CONFIG_QUICC_ENGINE
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if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
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qe_reset();
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of_node_put(np);
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!np) {
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np = of_find_node_by_name(NULL, "qe");
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if (!np)
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return;
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}
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if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
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struct device_node *ucc = NULL;
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qe_reset();
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of_node_put(np);
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np = of_find_node_by_name(NULL, "par_io");
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if (np) {
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struct device_node *ucc;
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par_io_init(np);
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of_node_put(np);
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for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
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for_each_node_by_name(ucc, "ucc")
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par_io_of_config(ucc);
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of_node_put(ucc);
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}
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if (bcsr_regs) {
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@ -131,7 +135,6 @@ static void __init mpc85xx_mds_setup_arch(void)
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iounmap(bcsr_regs);
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}
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#endif /* CONFIG_QUICC_ENGINE */
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}
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@ -139,6 +142,7 @@ static struct of_device_id mpc85xx_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "qe", },
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{ .compatible = "fsl,qe", },
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{},
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};
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@ -176,10 +180,12 @@ static void __init mpc85xx_mds_pic_init(void)
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mpic_init(mpic);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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@ -1276,7 +1276,10 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
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const u32 *sysclk;
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/* SPI controller is either clocked from QE or SoC clock */
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np = of_find_node_by_type(NULL, "qe");
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!np)
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np = of_find_node_by_type(NULL, "qe");
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if (!np)
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np = of_find_node_by_type(NULL, "soc");
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@ -65,17 +65,22 @@ static phys_addr_t qebase = -1;
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phys_addr_t get_qe_base(void)
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{
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struct device_node *qe;
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unsigned int size;
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const void *prop;
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if (qebase != -1)
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return qebase;
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qe = of_find_node_by_type(NULL, "qe");
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if (qe) {
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unsigned int size;
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const void *prop = of_get_property(qe, "reg", &size);
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qebase = of_translate_address(qe, prop);
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of_node_put(qe);
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};
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qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!qe) {
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qe = of_find_node_by_type(NULL, "qe");
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if (!qe)
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return qebase;
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}
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prop = of_get_property(qe, "reg", &size);
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qebase = of_translate_address(qe, prop);
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of_node_put(qe);
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return qebase;
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}
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@ -153,16 +158,26 @@ static unsigned int brg_clk = 0;
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unsigned int get_brg_clk(void)
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{
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struct device_node *qe;
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unsigned int size;
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const u32 *prop;
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if (brg_clk)
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return brg_clk;
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qe = of_find_node_by_type(NULL, "qe");
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if (qe) {
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unsigned int size;
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const u32 *prop = of_get_property(qe, "brg-frequency", &size);
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brg_clk = *prop;
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of_node_put(qe);
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};
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qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!qe) {
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qe = of_find_node_by_type(NULL, "qe");
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if (!qe)
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return brg_clk;
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}
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prop = of_get_property(qe, "brg-frequency", &size);
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if (!prop || size != sizeof(*prop))
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return brg_clk;
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brg_clk = *prop;
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of_node_put(qe);
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return brg_clk;
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}
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@ -322,7 +337,7 @@ static rh_info_t qe_muram_info;
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static void qe_muram_init(void)
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{
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struct device_node *np;
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u32 address;
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const u32 *address;
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u64 size;
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unsigned int flags;
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@ -335,11 +350,21 @@ static void qe_muram_init(void)
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/* XXX: This is a subset of the available muram. It
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* varies with the processor and the microcode patches activated.
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*/
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if ((np = of_find_node_by_name(NULL, "data-only")) != NULL) {
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address = *of_get_address(np, 0, &size, &flags);
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of_node_put(np);
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rh_attach_region(&qe_muram_info, address, (int) size);
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-muram-data");
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if (!np) {
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np = of_find_node_by_name(NULL, "data-only");
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if (!np) {
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WARN_ON(1);
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return;
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}
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}
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address = of_get_address(np, 0, &size, &flags);
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WARN_ON(!address);
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of_node_put(np);
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if (address)
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rh_attach_region(&qe_muram_info, *address, (int)size);
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}
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/* This function returns an index into the MURAM area.
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