forked from luck/tmp_suning_uos_patched
OMAP2/3: GPMC: put sync_clk value in picoseconds instead of nanoseconds
The calculations done with sync_clk are anyway in picoseconds and switching to picoseconds allows sync_clk values that are not a whole number of nanoseconds - which is sometimes the case. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -41,7 +41,7 @@ static int omap2_nand_gpmc_retime(void)
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return 0;
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memset(&t, 0, sizeof(t));
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t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk);
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t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk;
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t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
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t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on);
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@ -174,7 +174,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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switch (freq) {
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case 83:
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min_gpmc_clk_period = 12; /* 83 MHz */
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min_gpmc_clk_period = 12000; /* 83 MHz */
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t_ces = 5;
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t_avds = 4;
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t_avdh = 2;
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@ -183,7 +183,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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t_rdyo = 9;
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break;
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case 66:
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min_gpmc_clk_period = 15; /* 66 MHz */
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min_gpmc_clk_period = 15000; /* 66 MHz */
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t_ces = 6;
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t_avds = 5;
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t_avdh = 2;
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@ -192,7 +192,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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t_rdyo = 11;
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break;
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default:
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min_gpmc_clk_period = 18; /* 54 MHz */
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min_gpmc_clk_period = 18500; /* 54 MHz */
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t_ces = 7;
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t_avds = 7;
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t_avdh = 7;
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@ -271,8 +271,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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t.wr_cycle = t.rd_cycle;
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if (cpu_is_omap34xx()) {
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t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
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gpmc_ns_to_ticks(min_gpmc_clk_period +
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t_rdyo));
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gpmc_ps_to_ticks(min_gpmc_clk_period +
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t_rdyo * 1000));
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t.wr_access = t.access;
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}
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} else {
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@ -168,6 +168,16 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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return (time_ns * 1000 + tick_ps - 1) / tick_ps;
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}
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unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
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{
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unsigned long tick_ps;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = gpmc_get_fclk_period();
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return (time_ps + tick_ps - 1) / tick_ps;
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}
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unsigned int gpmc_ticks_to_ns(unsigned int ticks)
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{
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return ticks * gpmc_get_fclk_period() / 1000;
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@ -235,7 +245,7 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
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int div;
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u32 l;
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l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
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l = sync_clk + (gpmc_get_fclk_period() - 1);
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div = l / gpmc_get_fclk_period();
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if (div > 4)
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return -1;
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@ -120,8 +120,8 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
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t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps);
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/* GPMC_CLK rate = fclk rate / div */
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t.sync_clk = 12 /* 11.1 nsec */;
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tmp = (t.sync_clk * 1000 + fclk_ps - 1) / fclk_ps;
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t.sync_clk = 11100 /* 11.1 nsec */;
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tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
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if (tmp > 4)
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return -ERANGE;
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if (tmp <= 0)
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@ -80,12 +80,12 @@
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#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
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/*
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* Note that all values in this struct are in nanoseconds, while
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* the register values are in gpmc_fck cycles.
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* Note that all values in this struct are in nanoseconds except sync_clk
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* (which is in picoseconds), while the register values are in gpmc_fck cycles.
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*/
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struct gpmc_timings {
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/* Minimum clock period for synchronous mode */
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u16 sync_clk;
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/* Minimum clock period for synchronous mode (in picoseconds) */
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u32 sync_clk;
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/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
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u16 cs_on; /* Assertion time */
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@ -117,6 +117,7 @@ struct gpmc_timings {
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};
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extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
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extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
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extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
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extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
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extern unsigned long gpmc_get_fclk_period(void);
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