forked from luck/tmp_suning_uos_patched
sh: update sh7343 code
updated the following codes for SH7343: - add register_intc_controller() - add EARLY_SCIF_CONSOLE_PORT - add define of CPG register Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Yoshihiro Shimoda
Paul Mundt
parent
73382f710b
commit
a4e1d08491
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@ -36,7 +36,8 @@ config EARLY_SCIF_CONSOLE_PORT
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default "0xff804000" if CPU_SUBTYPE_MXG
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default "0xffc30000" if CPU_SUBTYPE_SHX3
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default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
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CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
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CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
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CPU_SUBTYPE_SH7343
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default "0xffe80000" if CPU_SH4
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default "0xffea0000" if CPU_SUBTYPE_SH7785
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default "0xfffe8000" if CPU_SUBTYPE_SH7203
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@ -84,6 +84,141 @@ static int __init sh7343_devices_setup(void)
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}
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__initcall(sh7343_devices_setup);
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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DMAC0, DMAC1, DMAC2, DMAC3,
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VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
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MFI, VPU, TPU, Z3D4, USBI0, USBI1,
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MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
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DMAC4, DMAC5, DMAC_DADERR,
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KEYSC,
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SCIF, SCIF1, SCIF2, SCIF3, SCIF4,
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SIOF0, SIOF1, SIO,
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FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
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I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
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I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
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SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
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IRDA,
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SDHI0, SDHI1, SDHI2, SDHI3,
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CMT, TSIF, SIU,
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TMU0, TMU1, TMU2,
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JPU, LCDC,
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/* interrupt groups */
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DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
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INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
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INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
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INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
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INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
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INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
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INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
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INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
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INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
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INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
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INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
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INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
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INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
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INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
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INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
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INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
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INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
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INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
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INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
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INTC_VECT(SIO, 0xd00),
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INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
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INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
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INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
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INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
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INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
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INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
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INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
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INTC_VECT(SIU, 0xf80),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440),
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INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
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INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
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INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
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INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
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INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
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FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
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INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
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INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
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INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
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INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
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INTC_GROUP(USB, USBI0, USBI1),
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
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{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
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{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
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{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
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{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
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{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
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{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
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{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
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{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
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{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
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{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
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{ 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
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{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
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{ I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
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FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
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{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
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{ SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
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{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
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{ 0, 0, 0, CMT, 0, USBI1, USBI0 } },
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{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
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{ MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
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{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
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{ I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
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{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
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{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
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{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
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{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
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{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
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{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
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{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
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{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
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{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
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{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
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{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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static struct intc_sense_reg sense_registers[] __initdata = {
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{ 0xa414001c, 16, 2, /* ICR1 */
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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static struct intc_mask_reg ack_registers[] __initdata = {
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{ 0xa4140024, 0, 8, /* INTREQ00 */
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
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mask_registers, prio_registers, sense_registers,
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ack_registers);
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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@ -12,6 +12,7 @@
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#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
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defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7343) || \
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defined(CONFIG_CPU_SUBTYPE_SH7366)
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#define FRQCR 0xa4150000
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#define VCLKCR 0xa4150004
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