forked from luck/tmp_suning_uos_patched
ARC updates for 4.11 rc1
- Intc imporvements [Yuriy] - VDK platform updates [Alexey] -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYrci0AAoJEGnX8d3iisJeNYcQAI3QH6jYnqb27viEqZ0jmTcC ItrxiD6L6oeiSYRZg9lY/4FwwiQUDhM3/Kt/+hGhLz1SBqjXGJ79DgtVyRTdHh+m nNiNrDVbFuiV6P8KbZX85tjW5QJI2HuahUoxyGNvnFG1k6vujmHuKBYm7eNz7XuM +18t89xqeQs7oluPX/MhuhfGwMzxscK69hT100WclYv/k2+mpU1fN/19Ygaw+IKJ p5HpxWj8WjyZ+4yODaqrZhFSwyOp8a+2nIMSPu0LIq+tg3a+kj+yACZfdmV+WbuD WncqI+tVzevk45BjSOH/3s1WOmNqAJswADpLS7AjVs/UmrK77UkQwRNo1jtEIz6Y XaCRuebCtWtoTDd1B44eHQNVStrQCnapjuUlTy7iFDwd/ldexrKFRO0DrvUvx652 XFgSY0BWyc3rnlckDugKixG6RnqY0jsGEaJAe2hNaMS3t87Pt1vNZ6y+75v0917F cG+rShA6GQ1vBaed+vWG8ocnKCfrzYsAODOBSko16KUdZsKTDIXCTMunFASr7Erg Z2wY4ntXVgRRhVCZX7poICwPnlvxKZrQfbbR7i+Z0Jmnuog1yEMMkUwK6Cn3cHoX mvQgPF1+XNGL0/8cXDuFGYyVKSpD6/Vc1z3bTjkjxy43Amys4faPFinXvZH7nJLK I/4jBW4+0QI38PxQFcfA =WPBu -----END PGP SIGNATURE----- Merge tag 'arc-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: - Intc imporvements [Yuriy] - VDK platform updates [Alexey] * tag 'arc-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant ARCv2: intc: Delete useless comments in Device Trees ARCv2: IDU-intc: Delete deprecated parameters in Device Trees ARCv2: IDU-intc: mask all common interrupts by default ARCv2: IDU-intc: Use build registers for getting numbers of interrupts ARCv2: intc: Set default priority for all core interrupts ARCv2: intc: Use runtime value of irq count for setting up intc ARCv2: intc: Rework the build time irq count information ARC: [intc-*]: confine NR_CPU_IRQS to intc code ARCv2: intc: Use ARC_REG_STATUS32 for addressing STATUS32 reg arc: vdk: Add support of UIO arc: vdk: Add support of MMC controller arc: vdk: Disable halt on reset
This commit is contained in:
Linus Torvalds
commit
a4ee7bacd6
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@ -8,15 +8,11 @@ Properties:
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- compatible: "snps,archs-idu-intc"
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- interrupt-controller: This is an interrupt controller.
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- interrupt-parent: <reference to parent core intc>
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- #interrupt-cells: Must be <2>.
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- interrupts: <...> specifies the upstream core irqs
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- #interrupt-cells: Must be <1>.
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First cell specifies the "common" IRQ from peripheral to IDU
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Second cell specifies the irq distribution mode to cores
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0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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The second cell in interrupts property is deprecated and may be ignored by
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the kernel.
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Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
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of the particular interrupt line of IDU corresponds to the line N+24 of the
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core interrupt controller.
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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@ -32,18 +28,10 @@ Example:
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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/* upstream core irqs: downstream these are "COMMON" irq 0,1.. */
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interrupts = <24 25 26 27 28 29 30 31>;
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#interrupt-cells = <1>;
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};
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some_device: serial@c0fc1000 {
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interrupt-parent = <&idu_intc>;
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interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */
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interrupts = <0>; /* upstream idu IRQ #24 */
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};
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@ -180,16 +180,12 @@ config CPU_BIG_ENDIAN
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config SMP
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bool "Symmetric Multi-Processing"
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default n
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select ARC_HAS_COH_CACHES if ISA_ARCV2
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select ARC_MCIP if ISA_ARCV2
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help
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This enables support for systems with more than one CPU.
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if SMP
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config ARC_HAS_COH_CACHES
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def_bool n
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config NR_CPUS
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int "Maximum number of CPUs (2-4096)"
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range 2 4096
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@ -219,8 +215,6 @@ config ARC_MCIP
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menuconfig ARC_CACHE
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bool "Enable Cache Support"
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default y
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# if SMP, cache enabled ONLY if ARC implementation has cache coherency
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depends on !SMP || ARC_HAS_COH_CACHES
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if ARC_CACHE
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@ -412,17 +406,6 @@ config ARC_HAS_DIV_REM
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bool "Insn: div, divu, rem, remu"
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default y
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config ARC_NUMBER_OF_INTERRUPTS
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int "Number of interrupts"
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range 8 240
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default 32
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help
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This defines the number of interrupts on the ARCv2HS core.
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It affects the size of vector table.
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The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
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in hardware, it keep things simple for Linux to assume they are always
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present.
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endif # ISA_ARCV2
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endmenu # "ARC CPU Configuration"
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@ -40,18 +40,7 @@ idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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/*
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* upstream irqs to core intc - downstream these are
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* "COMMON" irq 0,1..
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*/
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interrupts = <24 25>;
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#interrupt-cells = <1>;
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};
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/*
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@ -73,12 +62,7 @@ ictl_intc: gpio-controller@0 {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&idu_intc>;
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/*
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* cmn irq 1 -> cpu irq 25
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* Distribute to cpu0 only
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*/
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interrupts = <1 1>;
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interrupts = <1>;
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};
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};
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@ -119,8 +103,7 @@ mb_intc: dw-apb-ictl@0xe0012000 {
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reg = < 0xe0012000 0x200 >;
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interrupt-controller;
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interrupt-parent = <&idu_intc>;
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interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24
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distribute to cpu0 only */
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interrupts = <0>;
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};
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memory {
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@ -47,18 +47,13 @@ core_intc: interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/* <hwirq distribution>
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distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */
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#interrupt-cells = <2>;
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interrupts = <24 25 26 27 28 29 30 31>;
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#interrupt-cells = <1>;
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};
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uart0: serial@f0000000 {
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@ -66,9 +61,7 @@ uart0: serial@f0000000 {
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compatible = "ns16550a";
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reg = <0xf0000000 0x2000>;
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interrupt-parent = <&idu_intc>;
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/* interrupts = <0 1>; DEST=1*/
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/* interrupts = <0 2>; DEST=2*/
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interrupts = <0 0>; /* RR*/
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interrupts = <0>;
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clock-frequency = <50000000>;
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baud = <115200>;
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reg-shift = <2>;
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@ -46,25 +46,14 @@ idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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/*
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* upstream irqs to core intc - downstream these are
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* "COMMON" irq 0,1..
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*/
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interrupts = <24 25 26 27 28 29 30 31>;
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#interrupt-cells = <1>;
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};
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arcuart0: serial@c0fc1000 {
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compatible = "snps,arc-uart";
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reg = <0xc0fc1000 0x100>;
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interrupt-parent = <&idu_intc>;
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interrupts = <0 0>;
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interrupts = <0>;
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clock-frequency = <80000000>;
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current-speed = <115200>;
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status = "okay";
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@ -43,33 +43,20 @@ core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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/*
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* upstream irqs to core intc - downstream these are
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* "COMMON" irq 0,1..
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*/
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interrupts = <24 25 26 27 28 29 30 31>;
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#interrupt-cells = <1>;
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};
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uart0: serial@f0000000 {
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compatible = "ns8250";
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reg = <0xf0000000 0x2000>;
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interrupt-parent = <&idu_intc>;
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interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24
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RR distribute to all cpus */
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interrupts = <0>;
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clock-frequency = <3686400>;
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baud = <115200>;
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reg-shift = <2>;
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@ -93,7 +80,7 @@ pgu@f9000000 {
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ps2: ps2@f9001000 {
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compatible = "snps,arc_ps2";
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reg = <0xf9000400 0x14>;
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interrupts = <3 0>;
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interrupts = <3>;
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interrupt-parent = <&idu_intc>;
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interrupt-names = "arc_ps2_irq";
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};
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@ -102,7 +89,7 @@ eth0: ethernet@f0003000 {
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compatible = "ezchip,nps-mgt-enet";
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reg = <0xf0003000 0x44>;
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interrupt-parent = <&idu_intc>;
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interrupts = <1 2>;
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interrupts = <1>;
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};
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arcpct0: pct {
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@ -41,14 +41,7 @@ idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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interrupts = <24 25 26 27>;
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#interrupt-cells = <1>;
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};
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debug_uart: dw-apb-uart@0x5000 {
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@ -56,7 +49,7 @@ debug_uart: dw-apb-uart@0x5000 {
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reg = <0x5000 0x100>;
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clock-frequency = <2403200>;
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interrupt-parent = <&idu_intc>;
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interrupts = <2 0>;
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interrupts = <2>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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@ -70,7 +63,7 @@ mb_intc: dw-apb-ictl@0xe0012000 {
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reg = < 0xe0012000 0x200 >;
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interrupt-controller;
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interrupt-parent = <&idu_intc>;
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interrupts = < 0 0 >;
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interrupts = <0>;
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};
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memory {
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@ -23,6 +23,12 @@ apbclk: apbclk {
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#clock-cells = <0>;
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};
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mmcclk: mmcclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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pguclk: pguclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -94,5 +100,25 @@ ps2: ps2@e0017400 {
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interrupts = <5>;
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interrupt-names = "arc_ps2_irq";
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};
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mmc@0x15000 {
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compatible = "snps,dw-mshc";
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reg = <0x15000 0x400>;
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num-slots = <1>;
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fifo-depth = <1024>;
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card-detect-delay = <200>;
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clocks = <&apbclk>, <&mmcclk>;
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clock-names = "biu", "ciu";
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interrupts = <7>;
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bus-width = <4>;
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};
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/* Embedded Vision subsystem UIO mappings; only relevant for EV VDK */
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uio_ev: uio@0xD0000000 {
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compatible = "generic-uio";
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reg = <0xD0000000 0x2000 0xD1000000 0x2000 0x90000000 0x10000000 0xC0000000 0x10000000>;
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reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
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interrupts = <23>;
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};
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};
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};
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@ -16,6 +16,7 @@ CONFIG_AXS103=y
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CONFIG_ISA_ARCV2=y
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CONFIG_SMP=y
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# CONFIG_ARC_TIMERS_64BIT is not set
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# CONFIG_ARC_SMP_HALT_ON_RESET is not set
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CONFIG_ARC_UBOOT_SUPPORT=y
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CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"
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CONFIG_PREEMPT=y
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|
@ -56,7 +57,6 @@ CONFIG_NATIONAL_PHY=y
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CONFIG_MOUSE_PS2_TOUCHKIT=y
|
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CONFIG_SERIO_ARC_PS2=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
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CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
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CONFIG_SERIAL_8250_DW=y
|
||||
|
|
@ -78,9 +78,14 @@ CONFIG_USB_OHCI_HCD=y
|
|||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_STORAGE=y
|
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CONFIG_USB_SERIAL=y
|
||||
CONFIG_MMC=y
|
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CONFIG_MMC_SDHCI=y
|
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CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_DW=y
|
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CONFIG_UIO=y
|
||||
CONFIG_UIO_PDRV_GENIRQ=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
|
|
|
|||
|
|
@ -38,6 +38,9 @@
|
|||
#define ARC_REG_CLUSTER_BCR 0xcf
|
||||
#define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
|
||||
|
||||
/* Common for ARCompact and ARCv2 status register */
|
||||
#define ARC_REG_STATUS32 0x0A
|
||||
|
||||
/* status32 Bits Positions */
|
||||
#define STATUS_AE_BIT 5 /* Exception active */
|
||||
#define STATUS_DE_BIT 6 /* PC is in delay slot */
|
||||
|
|
|
|||
|
|
@ -9,13 +9,19 @@
|
|||
#ifndef __ASM_ARC_IRQ_H
|
||||
#define __ASM_ARC_IRQ_H
|
||||
|
||||
#define NR_CPU_IRQS 32 /* number of interrupt lines of ARC770 CPU */
|
||||
#define NR_IRQS 128 /* allow some CPU external IRQ handling */
|
||||
/*
|
||||
* ARCv2 can support 240 interrupts in the core interrupts controllers and
|
||||
* 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
|
||||
* configurations of boards.
|
||||
* This doesnt affect ARCompact, but we change it to same value
|
||||
*/
|
||||
#define NR_IRQS 512
|
||||
|
||||
/* Platform Independent IRQs */
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
#define IPI_IRQ 19
|
||||
#define SOFTIRQ_IRQ 21
|
||||
#define FIRST_EXT_IRQ 24
|
||||
#endif
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
|
|
|
|||
|
|
@ -14,6 +14,11 @@
|
|||
#include <asm/arcregs.h>
|
||||
#include <asm/irqflags.h>
|
||||
|
||||
; A maximum number of supported interrupts in the core interrupt controller.
|
||||
; This number is not equal to the maximum interrupt number (256) because
|
||||
; first 16 lines are reserved for exceptions and are not configurable.
|
||||
#define NR_CPU_IRQS 240
|
||||
|
||||
.cpu HS
|
||||
|
||||
#define VECTOR .word
|
||||
|
|
@ -52,7 +57,7 @@ VECTOR handle_interrupt ; unused
|
|||
VECTOR handle_interrupt ; (23) unused
|
||||
# End of fixed IRQs
|
||||
|
||||
.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8
|
||||
.rept NR_CPU_IRQS - 8
|
||||
VECTOR handle_interrupt
|
||||
.endr
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,16 @@
|
|||
#include <linux/irqchip.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#define NR_EXCEPTIONS 16
|
||||
|
||||
struct bcr_irq_arcv2 {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
|
||||
#else
|
||||
unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* Early Hardware specific Interrupt setup
|
||||
* -Called very early (start_kernel -> setup_arch -> setup_processor)
|
||||
|
|
@ -22,15 +32,8 @@
|
|||
*/
|
||||
void arc_init_IRQ(void)
|
||||
{
|
||||
unsigned int tmp, irq_prio;
|
||||
|
||||
struct irq_build {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
|
||||
#else
|
||||
unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
|
||||
#endif
|
||||
} irq_bcr;
|
||||
unsigned int tmp, irq_prio, i;
|
||||
struct bcr_irq_arcv2 irq_bcr;
|
||||
|
||||
struct aux_irq_ctrl {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
|
|
@ -68,8 +71,18 @@ void arc_init_IRQ(void)
|
|||
irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
|
||||
irq_bcr.firq ? " FIRQ (not used)":"");
|
||||
|
||||
/*
|
||||
* Set a default priority for all available interrupts to prevent
|
||||
* switching of register banks if Fast IRQ and multiple register banks
|
||||
* are supported by CPU.
|
||||
*/
|
||||
for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
|
||||
write_aux_reg(AUX_IRQ_SELECT, i);
|
||||
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
|
||||
}
|
||||
|
||||
/* setup status32, don't enable intr yet as kernel doesn't want */
|
||||
tmp = read_aux_reg(0xa);
|
||||
tmp = read_aux_reg(ARC_REG_STATUS32);
|
||||
tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
|
||||
tmp &= ~STATUS_IE_MASK;
|
||||
asm volatile("kflag %0 \n"::"r"(tmp));
|
||||
|
|
@ -115,7 +128,7 @@ static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
|
|||
* core intc IRQs [16, 23]:
|
||||
* Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
|
||||
*/
|
||||
if (hw < 24) {
|
||||
if (hw < FIRST_EXT_IRQ) {
|
||||
/*
|
||||
* A subsequent request_percpu_irq() fails if percpu_devid is
|
||||
* not set. That in turns sets NOAUTOEN, meaning each core needs
|
||||
|
|
@ -140,11 +153,16 @@ static int __init
|
|||
init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
|
||||
{
|
||||
struct irq_domain *root_domain;
|
||||
struct bcr_irq_arcv2 irq_bcr;
|
||||
unsigned int nr_cpu_irqs;
|
||||
|
||||
READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
|
||||
nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
|
||||
|
||||
if (parent)
|
||||
panic("DeviceTree incore intc not a root irq controller\n");
|
||||
|
||||
root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, &arcv2_irq_ops, NULL);
|
||||
root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
|
||||
if (!root_domain)
|
||||
panic("root irq domain not avail\n");
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/irqchip.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#define NR_CPU_IRQS 32 /* number of irq lines coming in */
|
||||
#define TIMER0_IRQ 3 /* Fixed by ISA */
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -156,15 +156,20 @@ static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
|
|||
__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
|
||||
}
|
||||
|
||||
static void idu_irq_mask(struct irq_data *data)
|
||||
static void idu_irq_mask_raw(irq_hw_number_t hwirq)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
|
||||
__mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1);
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
}
|
||||
|
||||
static void idu_irq_mask(struct irq_data *data)
|
||||
{
|
||||
idu_irq_mask_raw(data->hwirq);
|
||||
}
|
||||
|
||||
static void idu_irq_unmask(struct irq_data *data)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
|
@ -230,14 +235,12 @@ static struct irq_chip idu_irq_chip = {
|
|||
|
||||
};
|
||||
|
||||
static irq_hw_number_t idu_first_hwirq;
|
||||
|
||||
static void idu_cascade_isr(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *core_chip = irq_desc_get_chip(desc);
|
||||
irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
|
||||
irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
|
||||
irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
|
||||
|
||||
chained_irq_enter(core_chip, desc);
|
||||
generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
|
||||
|
|
@ -252,23 +255,8 @@ static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
|
||||
const u32 *intspec, unsigned int intsize,
|
||||
irq_hw_number_t *out_hwirq, unsigned int *out_type)
|
||||
{
|
||||
/*
|
||||
* Ignore value of interrupt distribution mode for common interrupts in
|
||||
* IDU which resides in intspec[1] since setting an affinity using value
|
||||
* from Device Tree is deprecated in ARC.
|
||||
*/
|
||||
*out_hwirq = intspec[0];
|
||||
*out_type = IRQ_TYPE_NONE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops idu_irq_ops = {
|
||||
.xlate = idu_irq_xlate,
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
.map = idu_irq_map,
|
||||
};
|
||||
|
||||
|
|
@ -283,33 +271,37 @@ static int __init
|
|||
idu_of_init(struct device_node *intc, struct device_node *parent)
|
||||
{
|
||||
struct irq_domain *domain;
|
||||
/* Read IDU BCR to confirm nr_irqs */
|
||||
int nr_irqs = of_irq_count(intc);
|
||||
int nr_irqs;
|
||||
int i, virq;
|
||||
struct mcip_bcr mp;
|
||||
struct mcip_idu_bcr idu_bcr;
|
||||
|
||||
READ_BCR(ARC_REG_MCIP_BCR, mp);
|
||||
|
||||
if (!mp.idu)
|
||||
panic("IDU not detected, but DeviceTree using it");
|
||||
|
||||
pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
|
||||
READ_BCR(ARC_REG_MCIP_IDU_BCR, idu_bcr);
|
||||
nr_irqs = mcip_idu_bcr_to_nr_irqs(idu_bcr);
|
||||
|
||||
pr_info("MCIP: IDU supports %u common irqs\n", nr_irqs);
|
||||
|
||||
domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
|
||||
|
||||
/* Parent interrupts (core-intc) are already mapped */
|
||||
|
||||
for (i = 0; i < nr_irqs; i++) {
|
||||
/* Mask all common interrupts by default */
|
||||
idu_irq_mask_raw(i);
|
||||
|
||||
/*
|
||||
* Return parent uplink IRQs (towards core intc) 24,25,.....
|
||||
* this step has been done before already
|
||||
* however we need it to get the parent virq and set IDU handler
|
||||
* as first level isr
|
||||
*/
|
||||
virq = irq_of_parse_and_map(intc, i);
|
||||
if (!i)
|
||||
idu_first_hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
|
||||
|
||||
virq = irq_create_mapping(NULL, i + FIRST_EXT_IRQ);
|
||||
BUG_ON(!virq);
|
||||
irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@
|
|||
|
||||
menuconfig ARC_PLAT_EZNPS
|
||||
bool "\"EZchip\" ARC dev platform"
|
||||
select ARC_HAS_COH_CACHES if SMP
|
||||
select CPU_BIG_ENDIAN
|
||||
select CLKSRC_NPS
|
||||
select EZNPS_GIC
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
menuconfig ARC_PLAT_SIM
|
||||
bool "ARC nSIM based simulation virtual platforms"
|
||||
select ARC_HAS_COH_CACHES if SMP
|
||||
help
|
||||
Support for nSIM based ARC simulation platforms
|
||||
This includes the standalone nSIM (uart only) vs. System C OSCI VP
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <soc/arc/aux.h>
|
||||
|
||||
#define ARC_REG_MCIP_BCR 0x0d0
|
||||
#define ARC_REG_MCIP_IDU_BCR 0x0D5
|
||||
#define ARC_REG_MCIP_CMD 0x600
|
||||
#define ARC_REG_MCIP_WDATA 0x601
|
||||
#define ARC_REG_MCIP_READBACK 0x602
|
||||
|
|
@ -69,6 +70,22 @@ struct mcip_bcr {
|
|||
#endif
|
||||
};
|
||||
|
||||
struct mcip_idu_bcr {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad:21, cirqnum:3, ver:8;
|
||||
#else
|
||||
unsigned int ver:8, cirqnum:3, pad:21;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Build register for IDU contains not an actual number of supported common
|
||||
* interrupts but an exponent of 2 which must be multiplied by 4 to
|
||||
* get a number of supported common interrupts.
|
||||
*/
|
||||
#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
|
||||
|
||||
/*
|
||||
* MCIP programming model
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user