forked from luck/tmp_suning_uos_patched
usb: musb: musb_cppi41: handle pre-mature TX complete interrupt
The TX-complete interrupt of the CPPI41 on AM335x fires too early. Adding a loop and counting how long it takes until the MUSB_TXCSR_TXPKTRDY bit is cleared I see FS: |musb-hdrc musb-hdrc.0.auto: configure ep1/80 packet_sz=64, mode=0, dma_addr=0xadc54002, len=1514 is_tx=1 |cppi41_dma_callback() 74 loops |musb-hdrc musb-hdrc.0.auto: configure ep1/80 packet_sz=64, mode=0, dma_addr=0xadcd8802, len=1514 is_tx=1 |cppi41_dma_callback() 66 loops |musb-hdrc musb-hdrc.0.auto: configure ep1/80 packet_sz=64, mode=0, dma_addr=0xadcd8002, len=1514 is_tx=1 |cppi41_dma_callback() 136 loops |musb-hdrc musb-hdrc.0.auto: configure ep1/80 packet_sz=64, mode=0, dma_addr=0xadf55802, len=1514 is_tx=1 |cppi41_dma_callback() 136 loops avg: 110 - 150us HS: |musb-hdrc musb-hdrc.0.auto: configure ep1/80 packet_sz=512, mode=0, dma_addr=0xaca6f002, len=1514 is_tx=1 |cppi41_dma_callback() 0 loops |musb-hdrc musb-hdrc.0.auto: configure ep1/80 packet_sz=512, mode=0, dma_addr=0xadd6f802, len=1514 is_tx=1 |cppi41_dma_callback() 2 loops |musb-hdrc musb-hdrc.0.auto: configure ep1/80 packet_sz=512, mode=0, dma_addr=0xadd6f002, len=1514 is_tx=1 |cppi41_dma_callback() 13 loops avg: 2us for the same test case. One loop means a udelay(1). The delay seems to depend on the packet size. On HS the bit is always cleared for small packet sizes while on FS it is never the case, it mostly around 110us. This testing has been performed with g_ether (musb as device) and using BULK transfers. INTR transfers are way more fun: during init the gadget sends a INT packet to the host and cppi41 says "transfer done" shortly after. The MUSB_TXCSR_TXPKTRDY bit is set even seconds later. The reason is that the host did not try to receive it, it does so after the interface (on host side) has been configured. Until this happens, that packet remains in musb's FIFO. To fix this, two things are done: - No DMA transfers for INT based endpoints. These transfer are usually very small and rare so it is likely better to skip the DMA engine and stuff the four bytes directly into the FIFO - on HS we poll up to 25us and hope that bit goes away. If not we setup a hrtimer to poll for it. The 140us delay is a rule of thumb. In FS the command | ping 10.10.10.10 -c1 -s65130 creates about 44 1514bytes transfers. About 19 of them need a second timer to complete. Reported-by: Bin Liu <b-liu@ti.com> Cc: stable@vger.kernel.org Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Sebastian Andrzej Siewior
Felipe Balbi
parent
d373a8534d
commit
a655f481d8
@ -38,6 +38,7 @@ struct cppi41_dma_channel {
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u32 prog_len;
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u32 transferred;
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u32 packet_sz;
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struct list_head tx_check;
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};
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#define MUSB_DMA_NUM_CHANNELS 15
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@ -47,6 +48,8 @@ struct cppi41_dma_controller {
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struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
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struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
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struct musb *musb;
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struct hrtimer early_tx;
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struct list_head early_tx_list;
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u32 rx_mode;
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u32 tx_mode;
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u32 auto_req;
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@ -96,11 +99,23 @@ static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
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cppi41_channel->usb_toggle = toggle;
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}
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static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
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{
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u8 epnum = hw_ep->epnum;
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struct musb *musb = hw_ep->musb;
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void __iomem *epio = musb->endpoints[epnum].regs;
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u16 csr;
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csr = musb_readw(epio, MUSB_TXCSR);
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if (csr & MUSB_TXCSR_TXPKTRDY)
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return false;
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return true;
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}
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static void cppi41_dma_callback(void *private_data);
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static void cppi41_trans_done(struct dma_channel *channel)
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static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
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{
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struct cppi41_dma_channel *cppi41_channel = channel->private_data;
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struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
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struct musb *musb = hw_ep->musb;
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@ -138,7 +153,7 @@ static void cppi41_trans_done(struct dma_channel *channel)
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return;
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dma_desc->callback = cppi41_dma_callback;
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dma_desc->callback_param = channel;
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dma_desc->callback_param = &cppi41_channel->channel;
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cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
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dma_async_issue_pending(dc);
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@ -150,6 +165,41 @@ static void cppi41_trans_done(struct dma_channel *channel)
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}
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}
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static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
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{
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struct cppi41_dma_controller *controller;
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struct cppi41_dma_channel *cppi41_channel, *n;
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struct musb *musb;
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unsigned long flags;
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enum hrtimer_restart ret = HRTIMER_NORESTART;
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controller = container_of(timer, struct cppi41_dma_controller,
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early_tx);
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musb = controller->musb;
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spin_lock_irqsave(&musb->lock, flags);
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list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
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tx_check) {
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bool empty;
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struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
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empty = musb_is_tx_fifo_empty(hw_ep);
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if (empty) {
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list_del_init(&cppi41_channel->tx_check);
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cppi41_trans_done(cppi41_channel);
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}
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}
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if (!list_empty(&controller->early_tx_list)) {
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ret = HRTIMER_RESTART;
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hrtimer_forward_now(&controller->early_tx,
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ktime_set(0, 150 * NSEC_PER_USEC));
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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return ret;
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}
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static void cppi41_dma_callback(void *private_data)
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{
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struct dma_channel *channel = private_data;
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@ -159,6 +209,7 @@ static void cppi41_dma_callback(void *private_data)
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unsigned long flags;
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struct dma_tx_state txstate;
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u32 transferred;
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bool empty;
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spin_lock_irqsave(&musb->lock, flags);
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@ -177,8 +228,52 @@ static void cppi41_dma_callback(void *private_data)
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transferred < cppi41_channel->packet_sz)
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cppi41_channel->prog_len = 0;
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cppi41_trans_done(channel);
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empty = musb_is_tx_fifo_empty(hw_ep);
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if (empty) {
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cppi41_trans_done(cppi41_channel);
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} else {
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struct cppi41_dma_controller *controller;
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/*
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* On AM335x it has been observed that the TX interrupt fires
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* too early that means the TXFIFO is not yet empty but the DMA
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* engine says that it is done with the transfer. We don't
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* receive a FIFO empty interrupt so the only thing we can do is
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* to poll for the bit. On HS it usually takes 2us, on FS around
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* 110us - 150us depending on the transfer size.
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* We spin on HS (no longer than than 25us and setup a timer on
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* FS to check for the bit and complete the transfer.
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*/
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controller = cppi41_channel->controller;
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if (musb->g.speed == USB_SPEED_HIGH) {
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unsigned wait = 25;
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do {
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empty = musb_is_tx_fifo_empty(hw_ep);
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if (empty)
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break;
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wait--;
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if (!wait)
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break;
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udelay(1);
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} while (1);
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empty = musb_is_tx_fifo_empty(hw_ep);
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if (empty) {
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cppi41_trans_done(cppi41_channel);
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goto out;
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}
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}
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list_add_tail(&cppi41_channel->tx_check,
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&controller->early_tx_list);
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if (!hrtimer_active(&controller->early_tx)) {
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hrtimer_start_range_ns(&controller->early_tx,
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ktime_set(0, 140 * NSEC_PER_USEC),
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40 * NSEC_PER_USEC,
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HRTIMER_MODE_REL);
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}
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}
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out:
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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@ -377,6 +472,8 @@ static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
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WARN_ON(1);
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return 1;
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}
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if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
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return 0;
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if (cppi41_channel->is_tx)
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return 1;
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/* AM335x Advisory 1.0.13. No workaround for device RX mode */
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@ -401,6 +498,7 @@ static int cppi41_dma_channel_abort(struct dma_channel *channel)
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if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
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return 0;
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list_del_init(&cppi41_channel->tx_check);
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if (is_tx) {
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csr = musb_readw(epio, MUSB_TXCSR);
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csr &= ~MUSB_TXCSR_DMAENAB;
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@ -508,6 +606,7 @@ static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
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cppi41_channel->controller = controller;
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cppi41_channel->port_num = port;
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cppi41_channel->is_tx = is_tx;
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INIT_LIST_HEAD(&cppi41_channel->tx_check);
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musb_dma = &cppi41_channel->channel;
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musb_dma->private_data = cppi41_channel;
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@ -533,6 +632,7 @@ void dma_controller_destroy(struct dma_controller *c)
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struct cppi41_dma_controller *controller = container_of(c,
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struct cppi41_dma_controller, controller);
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hrtimer_cancel(&controller->early_tx);
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cppi41_dma_controller_stop(controller);
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kfree(controller);
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}
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@ -552,6 +652,9 @@ struct dma_controller *dma_controller_create(struct musb *musb,
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if (!controller)
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goto kzalloc_fail;
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hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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controller->early_tx.function = cppi41_recheck_tx_req;
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INIT_LIST_HEAD(&controller->early_tx_list);
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controller->musb = musb;
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controller->controller.channel_alloc = cppi41_dma_channel_allocate;
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