forked from luck/tmp_suning_uos_patched
KVM: x86 emulator: add decoding of X,Y parameters from Intel SDM
Add decoding of X,Y parameters from Intel SDM which are used by string instruction to specify source and destination. Use this new decoding to implement movs, cmps, stos, lods in a generic way. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
This commit is contained in:
Gleb Natapov
Avi Kivity
parent
69f55cb11e
commit
a682e35449
@ -51,6 +51,7 @@
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#define DstReg (2<<1) /* Register operand. */
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#define DstMem (3<<1) /* Memory operand. */
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#define DstAcc (4<<1) /* Destination Accumulator */
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#define DstDI (5<<1) /* Destination is in ES:(E)DI */
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#define DstMask (7<<1)
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/* Source operand type. */
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#define SrcNone (0<<4) /* No source operand. */
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@ -64,6 +65,7 @@
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#define SrcOne (7<<4) /* Implied '1' */
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#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
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#define SrcImmU (9<<4) /* Immediate operand, unsigned */
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#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
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#define SrcMask (0xf<<4)
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/* Generic ModRM decode. */
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#define ModRM (1<<8)
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@ -177,12 +179,12 @@ static u32 opcode_table[256] = {
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/* 0xA0 - 0xA7 */
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ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
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ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
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ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
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ByteOp | ImplicitOps | String, ImplicitOps | String,
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ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
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ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
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/* 0xA8 - 0xAF */
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0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
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ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
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ByteOp | ImplicitOps | String, ImplicitOps | String,
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0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
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ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
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ByteOp | DstDI | String, DstDI | String,
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/* 0xB0 - 0xB7 */
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ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
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ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
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@ -1145,6 +1147,14 @@ x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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c->src.bytes = 1;
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c->src.val = 1;
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break;
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case SrcSI:
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c->src.type = OP_MEM;
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c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
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c->src.ptr = (unsigned long *)
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register_address(c, seg_override_base(ctxt, c),
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c->regs[VCPU_REGS_RSI]);
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c->src.val = 0;
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break;
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}
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/*
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@ -1230,6 +1240,14 @@ x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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}
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c->dst.orig_val = c->dst.val;
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break;
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case DstDI:
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c->dst.type = OP_MEM;
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c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
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c->dst.ptr = (unsigned long *)
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register_address(c, es_base(ctxt),
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c->regs[VCPU_REGS_RDI]);
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c->dst.val = 0;
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break;
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}
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done:
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@ -2392,6 +2410,16 @@ int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
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return rc;
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}
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static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
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int reg, unsigned long **ptr)
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{
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struct decode_cache *c = &ctxt->decode;
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int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
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register_address_increment(c, &c->regs[reg], df * c->src.bytes);
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*ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
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}
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int
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x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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{
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@ -2754,89 +2782,16 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
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break;
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case 0xa4 ... 0xa5: /* movs */
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c->dst.type = OP_MEM;
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c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
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c->dst.ptr = (unsigned long *)register_address(c,
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es_base(ctxt),
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c->regs[VCPU_REGS_RDI]);
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rc = ops->read_emulated(register_address(c,
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seg_override_base(ctxt, c),
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c->regs[VCPU_REGS_RSI]),
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&c->dst.val,
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c->dst.bytes, ctxt->vcpu);
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if (rc != X86EMUL_CONTINUE)
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goto done;
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register_address_increment(c, &c->regs[VCPU_REGS_RSI],
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(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
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: c->dst.bytes);
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register_address_increment(c, &c->regs[VCPU_REGS_RDI],
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(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
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: c->dst.bytes);
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break;
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goto mov;
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case 0xa6 ... 0xa7: /* cmps */
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c->src.type = OP_NONE; /* Disable writeback. */
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c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
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c->src.ptr = (unsigned long *)register_address(c,
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seg_override_base(ctxt, c),
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c->regs[VCPU_REGS_RSI]);
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rc = ops->read_emulated((unsigned long)c->src.ptr,
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&c->src.val,
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c->src.bytes,
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ctxt->vcpu);
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if (rc != X86EMUL_CONTINUE)
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goto done;
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c->dst.type = OP_NONE; /* Disable writeback. */
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c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
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c->dst.ptr = (unsigned long *)register_address(c,
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es_base(ctxt),
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c->regs[VCPU_REGS_RDI]);
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rc = ops->read_emulated((unsigned long)c->dst.ptr,
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&c->dst.val,
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c->dst.bytes,
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ctxt->vcpu);
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if (rc != X86EMUL_CONTINUE)
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goto done;
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DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
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emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
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register_address_increment(c, &c->regs[VCPU_REGS_RSI],
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(ctxt->eflags & EFLG_DF) ? -c->src.bytes
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: c->src.bytes);
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register_address_increment(c, &c->regs[VCPU_REGS_RDI],
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(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
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: c->dst.bytes);
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break;
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goto cmp;
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case 0xaa ... 0xab: /* stos */
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c->dst.type = OP_MEM;
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c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
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c->dst.ptr = (unsigned long *)register_address(c,
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es_base(ctxt),
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c->regs[VCPU_REGS_RDI]);
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c->dst.val = c->regs[VCPU_REGS_RAX];
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register_address_increment(c, &c->regs[VCPU_REGS_RDI],
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(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
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: c->dst.bytes);
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break;
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case 0xac ... 0xad: /* lods */
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c->dst.type = OP_REG;
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c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
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c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
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rc = ops->read_emulated(register_address(c,
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seg_override_base(ctxt, c),
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c->regs[VCPU_REGS_RSI]),
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&c->dst.val,
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c->dst.bytes,
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ctxt->vcpu);
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if (rc != X86EMUL_CONTINUE)
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goto done;
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register_address_increment(c, &c->regs[VCPU_REGS_RSI],
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(ctxt->eflags & EFLG_DF) ? -c->dst.bytes
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: c->dst.bytes);
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break;
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goto mov;
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case 0xae ... 0xaf: /* scas */
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DPRINTF("Urk! I don't handle SCAS.\n");
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goto cannot_emulate;
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@ -2979,6 +2934,14 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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if (rc != X86EMUL_CONTINUE)
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goto done;
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if ((c->d & SrcMask) == SrcSI)
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string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI,
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&c->src.ptr);
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if ((c->d & DstMask) == DstDI)
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string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI,
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&c->dst.ptr);
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/* Commit shadow register state. */
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memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
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kvm_rip_write(ctxt->vcpu, c->eip);
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