AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

ARM: S3C64XX: Add SROM register definitions

Browse Source 
This introduces a platform file for s3c64xx that defines
the SROM unit registers that control chip select
characteristics.

Signed-off-by: Andy Green <andy@warmcat.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Andy Green 2009-12-29 14:40:23 +00:00 committed by Ben Dooks
parent 0084f27a21
commit a7c9194cdc
2 changed files with 71 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/mach-s3c6400/include/mach/map.h
View File

@ -17,6 +17,18 @@
#include <plat/map-base.h> #include <plat/map-base.h>
/*
* Post-mux Chip Select Regions Xm0CSn_
* These may be used by SROM, NAND or CF depending on settings
*/
#define S3C64XX_PA_XM0CSN0 (0x10000000)
#define S3C64XX_PA_XM0CSN1 (0x18000000)
#define S3C64XX_PA_XM0CSN2 (0x20000000)
#define S3C64XX_PA_XM0CSN3 (0x28000000)
#define S3C64XX_PA_XM0CSN4 (0x30000000)
#define S3C64XX_PA_XM0CSN5 (0x38000000)
/* HSMMC units */ /* HSMMC units */
#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)

59
arch/arm/plat-s3c64xx/include/plat/regs-srom.h Normal file
View File

@ -0,0 +1,59 @@
/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
*
* Copyright 2009 Andy Green <andy@warmcat.com>
*
* S3C64XX SROM definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_SROM_H
#define __PLAT_REGS_SROM_H __FILE__
#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x))
#define S3C64XX_SROM_BW S3C64XX_SROMREG(0)
#define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4)
#define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8)
#define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc)
#define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10)
#define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14)
#define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18)
/*
* one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
*/
#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0
#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2
#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3
#define S3C64XX_SROM_BW__CS_MASK 0xf
#define S3C64XX_SROM_BW__NCS0__SHIFT 0
#define S3C64XX_SROM_BW__NCS1__SHIFT 4
#define S3C64XX_SROM_BW__NCS2__SHIFT 8
#define S3C64XX_SROM_BW__NCS3__SHIFT 0xc
#define S3C64XX_SROM_BW__NCS4__SHIFT 0x10
/*
* applies to same to BCS0 - BCS4
*/
#define S3C64XX_SROM_BCX__PMC__SHIFT 0
#define S3C64XX_SROM_BCX__PMC__MASK 3
#define S3C64XX_SROM_BCX__TACP__SHIFT 4
#define S3C64XX_SROM_BCX__TACP__MASK 0xf
#define S3C64XX_SROM_BCX__TCAH__SHIFT 8
#define S3C64XX_SROM_BCX__TCAH__MASK 0xf
#define S3C64XX_SROM_BCX__TCOH__SHIFT 12
#define S3C64XX_SROM_BCX__TCOH__MASK 0xf
#define S3C64XX_SROM_BCX__TACC__SHIFT 16
#define S3C64XX_SROM_BCX__TACC__MASK 0x1f
#define S3C64XX_SROM_BCX__TCOS__SHIFT 24
#define S3C64XX_SROM_BCX__TCOS__MASK 0xf
#define S3C64XX_SROM_BCX__TACS__SHIFT 28
#define S3C64XX_SROM_BCX__TACS__MASK 0xf
#endif /* _PLAT_REGS_SROM_H */