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MIPS: Actually decode JALX in `__compute_return_epc_for_insn'

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Complement commit fb6883e580 ("MIPS: microMIPS: Support handling of
delay slots.") and actually decode the regular MIPS JALX major
instruction opcode, the handling of which has been added with the said
commit for EPC calculation in `__compute_return_epc_for_insn'.

Fixes: fb6883e580 ("MIPS: microMIPS: Support handling of delay slots.")
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org # 3.9+
Patchwork: https://patchwork.linux-mips.org/patch/16394/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki 2017-06-16 00:06:19 +01:00 committed by Ralf Baechle
parent 13769ebad0
commit a9db101b73
1 changed files with 1 additions and 0 deletions
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arch/mips/kernel/branch.c
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@ -556,6 +556,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
/* /*
* These are unconditional and in j_format. * These are unconditional and in j_format.
*/ */
case jalx_op:
case jal_op: case jal_op:
regs->regs[31] = regs->cp0_epc + 8; regs->regs[31] = regs->cp0_epc + 8;
case j_op: case j_op: