forked from luck/tmp_suning_uos_patched
[POWERPC] fsl_lbc: implement few UPM routines
Freescale UPM can be used to adjust localbus timings or to generate orbitrary, pre-programmed "patterns" on the external Localbus signals. This patch implements few routines so drivers could work with UPMs in safe and generic manner. So far there is just one user of these routines: Freescale UPM NAND driver. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Anton Vorontsov
Kumar Gala
parent
d4a32fe40a
commit
acaa7aa30a
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@ -520,6 +520,11 @@ config FSL_PCI
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config 4xx_SOC
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bool
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config FSL_LBC
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bool
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help
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Freescale Localbus support
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# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
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config MCA
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bool
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@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_FSL_PCI) += fsl_pci.o
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obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
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obj-$(CONFIG_RAPIDIO) += fsl_rio.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
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129
arch/powerpc/sysdev/fsl_lbc.c
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129
arch/powerpc/sysdev/fsl_lbc.c
Normal file
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@ -0,0 +1,129 @@
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/*
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* Freescale LBC and UPM routines.
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*
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* Copyright (c) 2007-2008 MontaVista Software, Inc.
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <asm/fsl_lbc.h>
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spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
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struct fsl_lbc_regs __iomem *fsl_lbc_regs;
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EXPORT_SYMBOL(fsl_lbc_regs);
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static char __initdata *compat_lbc[] = {
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"fsl,pq2-localbus",
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"fsl,pq2pro-localbus",
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"fsl,pq3-localbus",
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"fsl,elbc",
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};
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static int __init fsl_lbc_init(void)
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{
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struct device_node *lbus;
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int i;
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for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
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lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
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if (lbus)
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goto found;
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}
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return -ENODEV;
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found:
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fsl_lbc_regs = of_iomap(lbus, 0);
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of_node_put(lbus);
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if (!fsl_lbc_regs)
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return -ENOMEM;
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return 0;
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}
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arch_initcall(fsl_lbc_init);
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/**
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* fsl_lbc_find - find Localbus bank
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* @addr_base: base address of the memory bank
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*
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* This function walks LBC banks comparing "Base address" field of the BR
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* registers with the supplied addr_base argument. When bases match this
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* function returns bank number (starting with 0), otherwise it returns
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* appropriate errno value.
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*/
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int fsl_lbc_find(phys_addr_t addr_base)
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{
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int i;
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if (!fsl_lbc_regs)
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return -ENODEV;
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for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
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__be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
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__be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
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if (br & BR_V && (br & or & BR_BA) == addr_base)
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return i;
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}
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return -ENOENT;
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}
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EXPORT_SYMBOL(fsl_lbc_find);
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/**
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* fsl_upm_find - find pre-programmed UPM via base address
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* @addr_base: base address of the memory bank controlled by the UPM
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* @upm: pointer to the allocated fsl_upm structure
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*
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* This function fills fsl_upm structure so you can use it with the rest of
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* UPM API. On success this function returns 0, otherwise it returns
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* appropriate errno value.
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*/
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int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
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{
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int bank;
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__be32 br;
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bank = fsl_lbc_find(addr_base);
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if (bank < 0)
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return bank;
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br = in_be32(&fsl_lbc_regs->bank[bank].br);
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switch (br & BR_MSEL) {
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case BR_MS_UPMA:
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upm->mxmr = &fsl_lbc_regs->mamr;
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break;
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case BR_MS_UPMB:
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upm->mxmr = &fsl_lbc_regs->mbmr;
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break;
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case BR_MS_UPMC:
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upm->mxmr = &fsl_lbc_regs->mcmr;
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break;
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default:
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return -EINVAL;
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}
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switch (br & BR_PS) {
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case BR_PS_8:
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upm->width = 8;
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break;
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case BR_PS_16:
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upm->width = 16;
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break;
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case BR_PS_32:
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upm->width = 32;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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EXPORT_SYMBOL(fsl_upm_find);
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@ -24,6 +24,8 @@
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#define __ASM_FSL_LBC_H
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <asm/io.h>
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struct fsl_lbc_bank {
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__be32 br; /**< Base Register */
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@ -98,6 +100,11 @@ struct fsl_lbc_regs {
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__be32 mar; /**< UPM Address Register */
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u8 res1[0x4];
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__be32 mamr; /**< UPMA Mode Register */
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#define MxMR_OP_NO (0 << 28) /**< normal operation */
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#define MxMR_OP_WA (1 << 28) /**< write array */
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#define MxMR_OP_RA (2 << 28) /**< read array */
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#define MxMR_OP_RP (3 << 28) /**< run pattern */
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#define MxMR_MAD 0x3f /**< machine address */
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__be32 mbmr; /**< UPMB Mode Register */
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__be32 mcmr; /**< UPMC Mode Register */
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u8 res2[0x8];
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@ -220,4 +227,85 @@ struct fsl_lbc_regs {
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u8 res8[0xF00];
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};
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extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
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extern spinlock_t fsl_lbc_lock;
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/*
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* FSL UPM routines
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*/
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struct fsl_upm {
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__be32 __iomem *mxmr;
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int width;
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};
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extern int fsl_lbc_find(phys_addr_t addr_base);
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extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
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/**
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* fsl_upm_start_pattern - start UPM patterns execution
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* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
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* @pat_offset: UPM pattern offset for the command to be executed
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*
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* This routine programmes UPM so the next memory access that hits an UPM
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* will trigger pattern execution, starting at pat_offset.
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*/
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static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
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{
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clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
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}
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/**
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* fsl_upm_end_pattern - end UPM patterns execution
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* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
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*
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* This routine reverts UPM to normal operation mode.
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*/
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static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
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{
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clrbits32(upm->mxmr, MxMR_OP_RP);
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while (in_be32(upm->mxmr) & MxMR_OP_RP)
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cpu_relax();
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}
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/**
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* fsl_upm_run_pattern - actually run an UPM pattern
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* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
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* @io_base: remapped pointer to where memory access should happen
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* @mar: MAR register content during pattern execution
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*
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* This function triggers dummy write to the memory specified by the io_base,
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* thus UPM pattern actually executed. Note that mar usage depends on the
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* pre-programmed AMX bits in the UPM RAM.
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*/
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static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
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void __iomem *io_base, u32 mar)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&fsl_lbc_lock, flags);
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out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
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switch (upm->width) {
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case 8:
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out_8(io_base, 0x0);
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break;
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case 16:
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out_be16(io_base, 0x0);
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break;
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case 32:
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out_be32(io_base, 0x0);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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spin_unlock_irqrestore(&fsl_lbc_lock, flags);
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return ret;
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}
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#endif /* __ASM_FSL_LBC_H */
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