forked from luck/tmp_suning_uos_patched
MIPS: kernel: cps-vec: Replace "addi" with "addiu"
The "addi" instruction will trap on overflows which is not something we need in this code, so we replace that with "addiu". Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00430.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Cc: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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@ -99,11 +99,11 @@ not_nmi:
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xori t2, t1, 0x7
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beqz t2, 1f
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li t3, 32
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addi t1, t1, 1
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addiu t1, t1, 1
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sllv t1, t3, t1
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1: /* At this point t1 == I-cache sets per way */
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_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
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addi t2, t2, 1
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addiu t2, t2, 1
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mul t1, t1, t0
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mul t1, t1, t2
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@ -126,11 +126,11 @@ icache_done:
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xori t2, t1, 0x7
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beqz t2, 1f
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li t3, 32
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addi t1, t1, 1
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addiu t1, t1, 1
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sllv t1, t3, t1
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1: /* At this point t1 == D-cache sets per way */
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_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
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addi t2, t2, 1
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addiu t2, t2, 1
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mul t1, t1, t0
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mul t1, t1, t2
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@ -250,7 +250,7 @@ LEAF(mips_cps_core_init)
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mfc0 t0, CP0_MVPCONF0
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srl t0, t0, MVPCONF0_PVPE_SHIFT
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andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
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addi t7, t0, 1
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addiu t7, t0, 1
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/* If there's only 1, we're done */
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beqz t0, 2f
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@ -280,7 +280,7 @@ LEAF(mips_cps_core_init)
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mttc0 t0, CP0_TCHALT
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/* Next VPE */
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addi t5, t5, 1
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addiu t5, t5, 1
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slt t0, t5, t7
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bnez t0, 1b
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nop
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@ -317,7 +317,7 @@ LEAF(mips_cps_boot_vpes)
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mfc0 t1, CP0_MVPCONF0
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srl t1, t1, MVPCONF0_PVPE_SHIFT
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andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
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addi t1, t1, 1
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addiu t1, t1, 1
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/* Calculate a mask for the VPE ID from EBase.CPUNum */
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clz t1, t1
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@ -424,7 +424,7 @@ LEAF(mips_cps_boot_vpes)
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/* Next VPE */
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2: srl t6, t6, 1
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addi t5, t5, 1
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addiu t5, t5, 1
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bnez t6, 1b
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nop
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