forked from luck/tmp_suning_uos_patched
amd64_edac: Carve out ECC-related hw settings
This is in preparation for the init path reorganization where we want only to 1) test whether a particular node supports ECC 2) can it be enabled and only then do the necessary allocation/initialization. For that, we need to decouple the ECC settings of the node from the instance's descriptor. The should be no functional change introduced by this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
parent
f1db274e1b
commit
ae7bb7c679
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@ -18,6 +18,7 @@ static struct msr __percpu *msrs;
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/* Per-node driver instances */
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static struct mem_ctl_info **mcis;
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static struct amd64_pvt **pvts;
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static struct ecc_settings **ecc_stngs;
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/*
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* Address to DRAM bank mapping: see F2x80 for K8 and F2x[1,0]80 for Fam10 and
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@ -2293,7 +2294,7 @@ static bool amd64_nb_mce_bank_enabled_on_node(int nid)
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return ret;
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}
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static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
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static int amd64_toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on)
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{
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cpumask_var_t cmask;
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int cpu;
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@ -2303,7 +2304,7 @@ static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
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return false;
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}
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get_cpus_on_this_dct_cpumask(cmask, pvt->mc_node_id);
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get_cpus_on_this_dct_cpumask(cmask, nid);
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rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
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@ -2313,14 +2314,14 @@ static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
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if (on) {
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if (reg->l & K8_MSR_MCGCTL_NBE)
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pvt->flags.nb_mce_enable = 1;
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s->flags.nb_mce_enable = 1;
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reg->l |= K8_MSR_MCGCTL_NBE;
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} else {
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/*
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* Turn off NB MCE reporting only when it was off before
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*/
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if (!pvt->flags.nb_mce_enable)
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if (!s->flags.nb_mce_enable)
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reg->l &= ~K8_MSR_MCGCTL_NBE;
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}
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}
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@ -2334,18 +2335,20 @@ static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
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static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u8 nid = pvt->mc_node_id;
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struct ecc_settings *s = ecc_stngs[nid];
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u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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amd64_read_pci_cfg(pvt->F3, K8_NBCTL, &value);
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/* turn on UECCn and CECCEn bits */
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pvt->old_nbctl = value & mask;
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pvt->nbctl_mcgctl_saved = 1;
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/* turn on UECCEn and CECCEn bits */
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s->old_nbctl = value & mask;
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s->nbctl_valid = true;
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value |= mask;
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pci_write_config_dword(pvt->F3, K8_NBCTL, value);
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if (amd64_toggle_ecc_err_reporting(pvt, ON))
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if (amd64_toggle_ecc_err_reporting(s, nid, ON))
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amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &value);
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@ -2357,7 +2360,7 @@ static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_warn("DRAM ECC disabled on this node, enabling...\n");
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pvt->flags.nb_ecc_prev = 0;
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s->flags.nb_ecc_prev = 0;
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/* Attempt to turn on DRAM ECC Enable */
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value |= K8_NBCFG_ECC_ENABLE;
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@ -2372,7 +2375,7 @@ static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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amd64_info("Hardware accepted DRAM ECC Enable\n");
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}
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} else {
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pvt->flags.nb_ecc_prev = 1;
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s->flags.nb_ecc_prev = 1;
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}
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debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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@ -2384,26 +2387,28 @@ static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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{
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u8 nid = pvt->mc_node_id;
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struct ecc_settings *s = ecc_stngs[nid];
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u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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if (!pvt->nbctl_mcgctl_saved)
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if (!s->nbctl_valid)
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return;
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amd64_read_pci_cfg(pvt->F3, K8_NBCTL, &value);
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value &= ~mask;
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value |= pvt->old_nbctl;
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value |= s->old_nbctl;
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pci_write_config_dword(pvt->F3, K8_NBCTL, value);
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/* restore previous BIOS DRAM ECC "off" setting which we force-enabled */
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if (!pvt->flags.nb_ecc_prev) {
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/* restore previous BIOS DRAM ECC "off" setting we force-enabled */
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if (!s->flags.nb_ecc_prev) {
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &value);
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value &= ~K8_NBCFG_ECC_ENABLE;
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pci_write_config_dword(pvt->F3, K8_NBCFG, value);
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}
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/* restore the NB Enable MCGCTL bit */
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if (amd64_toggle_ecc_err_reporting(pvt, OFF))
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if (amd64_toggle_ecc_err_reporting(s, nid, OFF))
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amd64_warn("Error restoring NB MCGCTL settings!\n");
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}
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@ -2654,6 +2659,8 @@ static int __devinit amd64_init_one_instance(struct pci_dev *pdev,
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const struct pci_device_id *mc_type)
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{
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int ret = 0;
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u8 nid = get_node_id(pdev);
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struct ecc_settings *s;
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ret = pci_enable_device(pdev);
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if (ret < 0) {
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@ -2661,9 +2668,16 @@ static int __devinit amd64_init_one_instance(struct pci_dev *pdev,
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return -EIO;
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}
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ret = -ENOMEM;
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s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
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if (!s)
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return ret;
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ecc_stngs[nid] = s;
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ret = amd64_probe_one_instance(pdev);
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if (ret < 0)
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amd64_err("Error probing instance: %d\n", get_node_id(pdev));
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amd64_err("Error probing instance: %d\n", nid);
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return ret;
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}
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@ -2688,6 +2702,9 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
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amd_report_gart_errors(false);
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amd_unregister_ecc_decoder(amd64_decode_bus_error);
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kfree(ecc_stngs[pvt->mc_node_id]);
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ecc_stngs[pvt->mc_node_id] = NULL;
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/* Free the EDAC CORE resources */
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mci->pvt_info = NULL;
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mcis[pvt->mc_node_id] = NULL;
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@ -2767,9 +2784,10 @@ static int __init amd64_edac_init(void)
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goto err_ret;
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err = -ENOMEM;
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pvts = kzalloc(amd_nb_num() * sizeof(pvts[0]), GFP_KERNEL);
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mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL);
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if (!(pvts && mcis))
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pvts = kzalloc(amd_nb_num() * sizeof(pvts[0]), GFP_KERNEL);
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mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL);
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ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL);
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if (!(pvts && mcis && ecc_stngs))
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goto err_ret;
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msrs = msrs_alloc();
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@ -2820,6 +2838,9 @@ static void __exit amd64_edac_exit(void)
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pci_unregister_driver(&amd64_pci_driver);
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kfree(ecc_stngs);
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ecc_stngs = NULL;
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kfree(mcis);
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mcis = NULL;
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@ -461,17 +461,21 @@ struct amd64_pvt {
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/* place to store error injection parameters prior to issue */
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struct error_injection injection;
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/* Save old hw registers' values before we modified them */
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u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
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u32 old_nbctl;
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/* DCT per-family scrubrate setting */
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u32 min_scrubrate;
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/* family name this instance is running on */
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const char *ctl_name;
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/* misc settings */
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};
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/*
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* per-node ECC settings descriptor
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*/
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struct ecc_settings {
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u32 old_nbctl;
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bool nbctl_valid;
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struct flags {
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unsigned long nb_mce_enable:1;
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unsigned long nb_ecc_prev:1;
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