forked from luck/tmp_suning_uos_patched
MIPS: GIC: Remove GIC_FLAG_IPI
irq-gic.c:gic_get_int() masks out interrupts from the pending set which aren’t in the pcpu_mask. Only interrupts marked with GIC_FLAG_IPI were set in pcpu_mask, meaning that peripheral interrupts also had to be marked as IPIs. Remove the use of GIC_FLAG_IPI and allow the flags member of struct gic_intr_map to be zero. Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7374/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -317,8 +317,7 @@ struct gic_intr_map {
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unsigned int polarity; /* Polarity : +/- */
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unsigned int trigtype; /* Trigger : Edge/Levl */
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unsigned int flags; /* Misc flags */
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#define GIC_FLAG_IPI 0x01
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#define GIC_FLAG_TRANSPARENT 0x02
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#define GIC_FLAG_TRANSPARENT 0x01
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};
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/*
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@ -311,9 +311,10 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
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/* Init Intr Masks */
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GIC_CLR_INTR_MASK(intr);
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/* Initialise per-cpu Interrupt software masks */
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if (flags & GIC_FLAG_IPI)
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set_bit(intr, pcpu_masks[cpu].pcpu_mask);
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set_bit(intr, pcpu_masks[cpu].pcpu_mask);
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if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
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GIC_SET_INTR_MASK(intr);
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if (trigtype == GIC_TRIG_EDGE)
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@ -352,8 +353,6 @@ static void __init gic_basic_init(int numintrs, int numvpes,
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cpu = intrmap[i].cpunum;
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if (cpu == GIC_UNUSED)
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continue;
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if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
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continue;
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gic_setup_intr(i,
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intrmap[i].cpunum,
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intrmap[i].pin + pin_offset,
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@ -427,7 +427,7 @@ static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
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gic_intr_map[intr].pin = cpupin;
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gic_intr_map[intr].polarity = GIC_POL_POS;
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gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
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gic_intr_map[intr].flags = GIC_FLAG_IPI;
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gic_intr_map[intr].flags = 0;
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ipi_map[cpu] |= (1 << (cpupin + 2));
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}
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