forked from luck/tmp_suning_uos_patched
dt-bindings: opp: Convert Allwinner H6 OPP to a schema
The Allwinner H6 SoCs use binning in order to provide binning to cpufreq which is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Maxime Ripard
Rob Herring
parent
90dc0d1ce8
commit
b30d8cf5e1
|
|
@ -0,0 +1,129 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner H6 CPU OPP Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
description: |
|
||||
For some SoCs, the CPU frequency subset and voltage value of each
|
||||
OPP varies based on the silicon variant in use. Allwinner Process
|
||||
Voltage Scaling Tables defines the voltage and frequency value based
|
||||
on the speedbin blown in the efuse combination. The
|
||||
sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
|
||||
provide the OPP framework with required information.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: allwinner,sun50i-h6-operating-points
|
||||
|
||||
nvmem-cells:
|
||||
description: |
|
||||
A phandle pointing to a nvmem-cells node representing the efuse
|
||||
registers that has information about the speedbin that is used
|
||||
to select the right frequency/voltage value pair. Please refer
|
||||
the for nvmem-cells bindings
|
||||
Documentation/devicetree/bindings/nvmem/nvmem.txt and also
|
||||
examples below.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- nvmem-cells
|
||||
|
||||
patternProperties:
|
||||
"opp-[0-9]+":
|
||||
type: object
|
||||
|
||||
properties:
|
||||
opp-hz: true
|
||||
|
||||
patternProperties:
|
||||
"opp-microvolt-.*": true
|
||||
|
||||
required:
|
||||
- opp-hz
|
||||
- opp-microvolt-speed0
|
||||
- opp-microvolt-speed1
|
||||
- opp-microvolt-speed2
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpu_opp_table: opp-table {
|
||||
compatible = "allwinner,sun50i-h6-operating-points";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-480000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <480000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000>;
|
||||
opp-microvolt-speed1 = <820000>;
|
||||
opp-microvolt-speed2 = <800000>;
|
||||
};
|
||||
|
||||
opp-720000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000>;
|
||||
opp-microvolt-speed1 = <820000>;
|
||||
opp-microvolt-speed2 = <800000>;
|
||||
};
|
||||
|
||||
opp-816000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <816000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000>;
|
||||
opp-microvolt-speed1 = <820000>;
|
||||
opp-microvolt-speed2 = <800000>;
|
||||
};
|
||||
|
||||
opp-888000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <888000000>;
|
||||
|
||||
opp-microvolt-speed0 = <940000>;
|
||||
opp-microvolt-speed1 = <820000>;
|
||||
opp-microvolt-speed2 = <800000>;
|
||||
};
|
||||
|
||||
opp-1080000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1080000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1060000>;
|
||||
opp-microvolt-speed1 = <880000>;
|
||||
opp-microvolt-speed2 = <840000>;
|
||||
};
|
||||
|
||||
opp-1320000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1320000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1160000>;
|
||||
opp-microvolt-speed1 = <940000>;
|
||||
opp-microvolt-speed2 = <900000>;
|
||||
};
|
||||
|
||||
opp-1488000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1488000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1160000>;
|
||||
opp-microvolt-speed1 = <1000000>;
|
||||
opp-microvolt-speed2 = <960000>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,167 +0,0 @@
|
|||
Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
|
||||
===================================
|
||||
|
||||
For some SoCs, the CPU frequency subset and voltage value of each OPP
|
||||
varies based on the silicon variant in use. Allwinner Process Voltage
|
||||
Scaling Tables defines the voltage and frequency value based on the
|
||||
speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver
|
||||
reads the efuse value from the SoC to provide the OPP framework with
|
||||
required information.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
In 'cpus' nodes:
|
||||
- operating-points-v2: Phandle to the operating-points-v2 table to use.
|
||||
|
||||
In 'operating-points-v2' table:
|
||||
- compatible: Should be
|
||||
- 'allwinner,sun50i-h6-operating-points'.
|
||||
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
|
||||
efuse registers that has information about the speedbin
|
||||
that is used to select the right frequency/voltage value
|
||||
pair. Please refer the for nvmem-cells bindings
|
||||
Documentation/devicetree/bindings/nvmem/nvmem.txt and
|
||||
also examples below.
|
||||
|
||||
In every OPP node:
|
||||
- opp-microvolt-<name>: Voltage in micro Volts.
|
||||
At runtime, the platform can pick a <name> and
|
||||
matching opp-microvolt-<name> property.
|
||||
[See: opp.txt]
|
||||
HW: <name>:
|
||||
sun50i-h6 speed0 speed1 speed2
|
||||
|
||||
Example 1:
|
||||
---------
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: opp_table {
|
||||
compatible = "allwinner,sun50i-h6-operating-points";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp@480000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <480000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000>;
|
||||
opp-microvolt-speed1 = <820000>;
|
||||
opp-microvolt-speed2 = <800000>;
|
||||
};
|
||||
|
||||
opp@720000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000>;
|
||||
opp-microvolt-speed1 = <820000>;
|
||||
opp-microvolt-speed2 = <800000>;
|
||||
};
|
||||
|
||||
opp@816000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <816000000>;
|
||||
|
||||
opp-microvolt-speed0 = <880000>;
|
||||
opp-microvolt-speed1 = <820000>;
|
||||
opp-microvolt-speed2 = <800000>;
|
||||
};
|
||||
|
||||
opp@888000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <888000000>;
|
||||
|
||||
opp-microvolt-speed0 = <940000>;
|
||||
opp-microvolt-speed1 = <820000>;
|
||||
opp-microvolt-speed2 = <800000>;
|
||||
};
|
||||
|
||||
opp@1080000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1080000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1060000>;
|
||||
opp-microvolt-speed1 = <880000>;
|
||||
opp-microvolt-speed2 = <840000>;
|
||||
};
|
||||
|
||||
opp@1320000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1320000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1160000>;
|
||||
opp-microvolt-speed1 = <940000>;
|
||||
opp-microvolt-speed2 = <900000>;
|
||||
};
|
||||
|
||||
opp@1488000000 {
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
opp-hz = /bits/ 64 <1488000000>;
|
||||
|
||||
opp-microvolt-speed0 = <1160000>;
|
||||
opp-microvolt-speed1 = <1000000>;
|
||||
opp-microvolt-speed2 = <960000>;
|
||||
};
|
||||
};
|
||||
....
|
||||
soc {
|
||||
....
|
||||
sid: sid@3006000 {
|
||||
compatible = "allwinner,sun50i-h6-sid";
|
||||
reg = <0x03006000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
....
|
||||
speedbin_efuse: speed@1c {
|
||||
reg = <0x1c 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user