forked from luck/tmp_suning_uos_patched
powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
Implement a POWER7 optimised memcpy using VMX and enhanced prefetch
instructions.
This is a copy of the POWER7 optimised copy_to_user/copy_from_user
loop. Detailed implementation and performance details can be found in
commit a66086b819 (powerpc: POWER7 optimised
copy_to_user/copy_from_user using VMX).
I noticed memcpy issues when profiling a RAID6 workload:
.memcpy
.async_memcpy
.async_copy_data
.__raid_run_ops
.handle_stripe
.raid5d
.md_thread
I created a simplified testcase by building a RAID6 array with 4 1GB
ramdisks (booting with brd.rd_size=1048576):
# mdadm -CR -e 1.2 /dev/md0 --level=6 -n4 /dev/ram[0-3]
I then timed how long it took to write to the entire array:
# dd if=/dev/zero of=/dev/md0 bs=1M
Before: 892 MB/s
After: 999 MB/s
A 12% improvement.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Anton Blanchard
Benjamin Herrenschmidt
parent
bce4b4bd91
commit
b3f271e86e
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@ -17,7 +17,8 @@ obj-$(CONFIG_HAS_IOMEM) += devres.o
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obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
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memcpy_64.o usercopy_64.o mem_64.o string.o \
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checksum_wrappers_64.o hweight_64.o \
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copyuser_power7.o string_64.o copypage_power7.o
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copyuser_power7.o string_64.o copypage_power7.o \
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memcpy_power7.o
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obj-$(CONFIG_XMON) += sstep.o ldstfp.o
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obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o
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obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o ldstfp.o
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@ -11,7 +11,11 @@
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.align 7
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_GLOBAL(memcpy)
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BEGIN_FTR_SECTION
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std r3,48(r1) /* save destination pointer for return value */
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FTR_SECTION_ELSE
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b memcpy_power7
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
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PPC_MTOCRF(0x01,r5)
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cmpldi cr1,r5,16
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neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
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650
arch/powerpc/lib/memcpy_power7.S
Normal file
650
arch/powerpc/lib/memcpy_power7.S
Normal file
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@ -0,0 +1,650 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) IBM Corporation, 2012
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*
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* Author: Anton Blanchard <anton@au.ibm.com>
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*/
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#include <asm/ppc_asm.h>
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#define STACKFRAMESIZE 256
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#define STK_REG(i) (112 + ((i)-14)*8)
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_GLOBAL(memcpy_power7)
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#ifdef CONFIG_ALTIVEC
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cmpldi r5,16
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cmpldi cr1,r5,4096
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std r3,48(r1)
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blt .Lshort_copy
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bgt cr1,.Lvmx_copy
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#else
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cmpldi r5,16
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std r3,48(r1)
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blt .Lshort_copy
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#endif
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.Lnonvmx_copy:
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/* Get the source 8B aligned */
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neg r6,r4
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mtocrf 0x01,r6
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clrldi r6,r6,(64-3)
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bf cr7*4+3,1f
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lbz r0,0(r4)
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addi r4,r4,1
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stb r0,0(r3)
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addi r3,r3,1
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1: bf cr7*4+2,2f
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lhz r0,0(r4)
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addi r4,r4,2
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sth r0,0(r3)
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addi r3,r3,2
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2: bf cr7*4+1,3f
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lwz r0,0(r4)
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addi r4,r4,4
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stw r0,0(r3)
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addi r3,r3,4
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3: sub r5,r5,r6
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cmpldi r5,128
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blt 5f
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mflr r0
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stdu r1,-STACKFRAMESIZE(r1)
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std r14,STK_REG(r14)(r1)
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std r15,STK_REG(r15)(r1)
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std r16,STK_REG(r16)(r1)
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std r17,STK_REG(r17)(r1)
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std r18,STK_REG(r18)(r1)
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std r19,STK_REG(r19)(r1)
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std r20,STK_REG(r20)(r1)
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std r21,STK_REG(r21)(r1)
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std r22,STK_REG(r22)(r1)
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std r0,STACKFRAMESIZE+16(r1)
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srdi r6,r5,7
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mtctr r6
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/* Now do cacheline (128B) sized loads and stores. */
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.align 5
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4:
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ld r0,0(r4)
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ld r6,8(r4)
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ld r7,16(r4)
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ld r8,24(r4)
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ld r9,32(r4)
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ld r10,40(r4)
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ld r11,48(r4)
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ld r12,56(r4)
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ld r14,64(r4)
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ld r15,72(r4)
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ld r16,80(r4)
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ld r17,88(r4)
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ld r18,96(r4)
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ld r19,104(r4)
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ld r20,112(r4)
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ld r21,120(r4)
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addi r4,r4,128
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std r0,0(r3)
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std r6,8(r3)
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std r7,16(r3)
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std r8,24(r3)
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std r9,32(r3)
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std r10,40(r3)
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std r11,48(r3)
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std r12,56(r3)
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std r14,64(r3)
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std r15,72(r3)
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std r16,80(r3)
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std r17,88(r3)
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std r18,96(r3)
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std r19,104(r3)
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std r20,112(r3)
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std r21,120(r3)
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addi r3,r3,128
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bdnz 4b
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clrldi r5,r5,(64-7)
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ld r14,STK_REG(r14)(r1)
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ld r15,STK_REG(r15)(r1)
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ld r16,STK_REG(r16)(r1)
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ld r17,STK_REG(r17)(r1)
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ld r18,STK_REG(r18)(r1)
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ld r19,STK_REG(r19)(r1)
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ld r20,STK_REG(r20)(r1)
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ld r21,STK_REG(r21)(r1)
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ld r22,STK_REG(r22)(r1)
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addi r1,r1,STACKFRAMESIZE
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/* Up to 127B to go */
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5: srdi r6,r5,4
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mtocrf 0x01,r6
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6: bf cr7*4+1,7f
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ld r0,0(r4)
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ld r6,8(r4)
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ld r7,16(r4)
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ld r8,24(r4)
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ld r9,32(r4)
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ld r10,40(r4)
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ld r11,48(r4)
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ld r12,56(r4)
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addi r4,r4,64
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std r0,0(r3)
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std r6,8(r3)
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std r7,16(r3)
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std r8,24(r3)
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std r9,32(r3)
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std r10,40(r3)
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std r11,48(r3)
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std r12,56(r3)
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addi r3,r3,64
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/* Up to 63B to go */
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7: bf cr7*4+2,8f
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ld r0,0(r4)
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ld r6,8(r4)
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ld r7,16(r4)
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ld r8,24(r4)
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addi r4,r4,32
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std r0,0(r3)
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std r6,8(r3)
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std r7,16(r3)
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std r8,24(r3)
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addi r3,r3,32
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/* Up to 31B to go */
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8: bf cr7*4+3,9f
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ld r0,0(r4)
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ld r6,8(r4)
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addi r4,r4,16
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std r0,0(r3)
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std r6,8(r3)
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addi r3,r3,16
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9: clrldi r5,r5,(64-4)
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/* Up to 15B to go */
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.Lshort_copy:
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mtocrf 0x01,r5
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bf cr7*4+0,12f
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lwz r0,0(r4) /* Less chance of a reject with word ops */
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lwz r6,4(r4)
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addi r4,r4,8
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stw r0,0(r3)
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stw r6,4(r3)
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addi r3,r3,8
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12: bf cr7*4+1,13f
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lwz r0,0(r4)
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addi r4,r4,4
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stw r0,0(r3)
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addi r3,r3,4
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13: bf cr7*4+2,14f
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lhz r0,0(r4)
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addi r4,r4,2
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sth r0,0(r3)
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addi r3,r3,2
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14: bf cr7*4+3,15f
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lbz r0,0(r4)
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stb r0,0(r3)
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15: ld r3,48(r1)
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blr
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.Lunwind_stack_nonvmx_copy:
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addi r1,r1,STACKFRAMESIZE
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b .Lnonvmx_copy
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#ifdef CONFIG_ALTIVEC
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.Lvmx_copy:
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mflr r0
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std r4,56(r1)
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std r5,64(r1)
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std r0,16(r1)
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stdu r1,-STACKFRAMESIZE(r1)
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bl .enter_vmx_copy
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cmpwi r3,0
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ld r0,STACKFRAMESIZE+16(r1)
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ld r3,STACKFRAMESIZE+48(r1)
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ld r4,STACKFRAMESIZE+56(r1)
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ld r5,STACKFRAMESIZE+64(r1)
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mtlr r0
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/*
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* We prefetch both the source and destination using enhanced touch
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* instructions. We use a stream ID of 0 for the load side and
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* 1 for the store side.
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*/
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clrrdi r6,r4,7
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clrrdi r9,r3,7
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ori r9,r9,1 /* stream=1 */
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srdi r7,r5,7 /* length in cachelines, capped at 0x3FF */
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cmpldi cr1,r7,0x3FF
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ble cr1,1f
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li r7,0x3FF
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1: lis r0,0x0E00 /* depth=7 */
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sldi r7,r7,7
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or r7,r7,r0
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ori r10,r7,1 /* stream=1 */
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lis r8,0x8000 /* GO=1 */
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clrldi r8,r8,32
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.machine push
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.machine "power4"
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dcbt r0,r6,0b01000
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dcbt r0,r7,0b01010
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dcbtst r0,r9,0b01000
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dcbtst r0,r10,0b01010
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eieio
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dcbt r0,r8,0b01010 /* GO */
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.machine pop
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beq .Lunwind_stack_nonvmx_copy
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/*
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* If source and destination are not relatively aligned we use a
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* slower permute loop.
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*/
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xor r6,r4,r3
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rldicl. r6,r6,0,(64-4)
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bne .Lvmx_unaligned_copy
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/* Get the destination 16B aligned */
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neg r6,r3
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mtocrf 0x01,r6
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clrldi r6,r6,(64-4)
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bf cr7*4+3,1f
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lbz r0,0(r4)
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addi r4,r4,1
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stb r0,0(r3)
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addi r3,r3,1
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1: bf cr7*4+2,2f
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lhz r0,0(r4)
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addi r4,r4,2
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sth r0,0(r3)
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addi r3,r3,2
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2: bf cr7*4+1,3f
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lwz r0,0(r4)
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addi r4,r4,4
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stw r0,0(r3)
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addi r3,r3,4
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3: bf cr7*4+0,4f
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ld r0,0(r4)
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addi r4,r4,8
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std r0,0(r3)
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addi r3,r3,8
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4: sub r5,r5,r6
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/* Get the desination 128B aligned */
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neg r6,r3
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srdi r7,r6,4
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mtocrf 0x01,r7
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clrldi r6,r6,(64-7)
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li r9,16
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li r10,32
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li r11,48
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bf cr7*4+3,5f
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lvx vr1,r0,r4
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addi r4,r4,16
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stvx vr1,r0,r3
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addi r3,r3,16
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5: bf cr7*4+2,6f
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lvx vr1,r0,r4
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lvx vr0,r4,r9
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addi r4,r4,32
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stvx vr1,r0,r3
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stvx vr0,r3,r9
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addi r3,r3,32
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6: bf cr7*4+1,7f
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lvx vr3,r0,r4
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lvx vr2,r4,r9
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lvx vr1,r4,r10
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lvx vr0,r4,r11
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addi r4,r4,64
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stvx vr3,r0,r3
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stvx vr2,r3,r9
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stvx vr1,r3,r10
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stvx vr0,r3,r11
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addi r3,r3,64
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7: sub r5,r5,r6
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srdi r6,r5,7
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std r14,STK_REG(r14)(r1)
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std r15,STK_REG(r15)(r1)
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std r16,STK_REG(r16)(r1)
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li r12,64
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li r14,80
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li r15,96
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li r16,112
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mtctr r6
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/*
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* Now do cacheline sized loads and stores. By this stage the
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* cacheline stores are also cacheline aligned.
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*/
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.align 5
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8:
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lvx vr7,r0,r4
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lvx vr6,r4,r9
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lvx vr5,r4,r10
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lvx vr4,r4,r11
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lvx vr3,r4,r12
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lvx vr2,r4,r14
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lvx vr1,r4,r15
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lvx vr0,r4,r16
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addi r4,r4,128
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stvx vr7,r0,r3
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stvx vr6,r3,r9
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stvx vr5,r3,r10
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stvx vr4,r3,r11
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stvx vr3,r3,r12
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stvx vr2,r3,r14
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stvx vr1,r3,r15
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stvx vr0,r3,r16
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addi r3,r3,128
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bdnz 8b
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ld r14,STK_REG(r14)(r1)
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ld r15,STK_REG(r15)(r1)
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ld r16,STK_REG(r16)(r1)
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/* Up to 127B to go */
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clrldi r5,r5,(64-7)
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srdi r6,r5,4
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mtocrf 0x01,r6
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bf cr7*4+1,9f
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lvx vr3,r0,r4
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lvx vr2,r4,r9
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lvx vr1,r4,r10
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lvx vr0,r4,r11
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addi r4,r4,64
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stvx vr3,r0,r3
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stvx vr2,r3,r9
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stvx vr1,r3,r10
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stvx vr0,r3,r11
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addi r3,r3,64
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9: bf cr7*4+2,10f
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lvx vr1,r0,r4
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lvx vr0,r4,r9
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addi r4,r4,32
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stvx vr1,r0,r3
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stvx vr0,r3,r9
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addi r3,r3,32
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10: bf cr7*4+3,11f
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lvx vr1,r0,r4
|
||||
addi r4,r4,16
|
||||
stvx vr1,r0,r3
|
||||
addi r3,r3,16
|
||||
|
||||
/* Up to 15B to go */
|
||||
11: clrldi r5,r5,(64-4)
|
||||
mtocrf 0x01,r5
|
||||
bf cr7*4+0,12f
|
||||
ld r0,0(r4)
|
||||
addi r4,r4,8
|
||||
std r0,0(r3)
|
||||
addi r3,r3,8
|
||||
|
||||
12: bf cr7*4+1,13f
|
||||
lwz r0,0(r4)
|
||||
addi r4,r4,4
|
||||
stw r0,0(r3)
|
||||
addi r3,r3,4
|
||||
|
||||
13: bf cr7*4+2,14f
|
||||
lhz r0,0(r4)
|
||||
addi r4,r4,2
|
||||
sth r0,0(r3)
|
||||
addi r3,r3,2
|
||||
|
||||
14: bf cr7*4+3,15f
|
||||
lbz r0,0(r4)
|
||||
stb r0,0(r3)
|
||||
|
||||
15: addi r1,r1,STACKFRAMESIZE
|
||||
ld r3,48(r1)
|
||||
b .exit_vmx_copy /* tail call optimise */
|
||||
|
||||
.Lvmx_unaligned_copy:
|
||||
/* Get the destination 16B aligned */
|
||||
neg r6,r3
|
||||
mtocrf 0x01,r6
|
||||
clrldi r6,r6,(64-4)
|
||||
|
||||
bf cr7*4+3,1f
|
||||
lbz r0,0(r4)
|
||||
addi r4,r4,1
|
||||
stb r0,0(r3)
|
||||
addi r3,r3,1
|
||||
|
||||
1: bf cr7*4+2,2f
|
||||
lhz r0,0(r4)
|
||||
addi r4,r4,2
|
||||
sth r0,0(r3)
|
||||
addi r3,r3,2
|
||||
|
||||
2: bf cr7*4+1,3f
|
||||
lwz r0,0(r4)
|
||||
addi r4,r4,4
|
||||
stw r0,0(r3)
|
||||
addi r3,r3,4
|
||||
|
||||
3: bf cr7*4+0,4f
|
||||
lwz r0,0(r4) /* Less chance of a reject with word ops */
|
||||
lwz r7,4(r4)
|
||||
addi r4,r4,8
|
||||
stw r0,0(r3)
|
||||
stw r7,4(r3)
|
||||
addi r3,r3,8
|
||||
|
||||
4: sub r5,r5,r6
|
||||
|
||||
/* Get the desination 128B aligned */
|
||||
neg r6,r3
|
||||
srdi r7,r6,4
|
||||
mtocrf 0x01,r7
|
||||
clrldi r6,r6,(64-7)
|
||||
|
||||
li r9,16
|
||||
li r10,32
|
||||
li r11,48
|
||||
|
||||
lvsl vr16,0,r4 /* Setup permute control vector */
|
||||
lvx vr0,0,r4
|
||||
addi r4,r4,16
|
||||
|
||||
bf cr7*4+3,5f
|
||||
lvx vr1,r0,r4
|
||||
vperm vr8,vr0,vr1,vr16
|
||||
addi r4,r4,16
|
||||
stvx vr8,r0,r3
|
||||
addi r3,r3,16
|
||||
vor vr0,vr1,vr1
|
||||
|
||||
5: bf cr7*4+2,6f
|
||||
lvx vr1,r0,r4
|
||||
vperm vr8,vr0,vr1,vr16
|
||||
lvx vr0,r4,r9
|
||||
vperm vr9,vr1,vr0,vr16
|
||||
addi r4,r4,32
|
||||
stvx vr8,r0,r3
|
||||
stvx vr9,r3,r9
|
||||
addi r3,r3,32
|
||||
|
||||
6: bf cr7*4+1,7f
|
||||
lvx vr3,r0,r4
|
||||
vperm vr8,vr0,vr3,vr16
|
||||
lvx vr2,r4,r9
|
||||
vperm vr9,vr3,vr2,vr16
|
||||
lvx vr1,r4,r10
|
||||
vperm vr10,vr2,vr1,vr16
|
||||
lvx vr0,r4,r11
|
||||
vperm vr11,vr1,vr0,vr16
|
||||
addi r4,r4,64
|
||||
stvx vr8,r0,r3
|
||||
stvx vr9,r3,r9
|
||||
stvx vr10,r3,r10
|
||||
stvx vr11,r3,r11
|
||||
addi r3,r3,64
|
||||
|
||||
7: sub r5,r5,r6
|
||||
srdi r6,r5,7
|
||||
|
||||
std r14,STK_REG(r14)(r1)
|
||||
std r15,STK_REG(r15)(r1)
|
||||
std r16,STK_REG(r16)(r1)
|
||||
|
||||
li r12,64
|
||||
li r14,80
|
||||
li r15,96
|
||||
li r16,112
|
||||
|
||||
mtctr r6
|
||||
|
||||
/*
|
||||
* Now do cacheline sized loads and stores. By this stage the
|
||||
* cacheline stores are also cacheline aligned.
|
||||
*/
|
||||
.align 5
|
||||
8:
|
||||
lvx vr7,r0,r4
|
||||
vperm vr8,vr0,vr7,vr16
|
||||
lvx vr6,r4,r9
|
||||
vperm vr9,vr7,vr6,vr16
|
||||
lvx vr5,r4,r10
|
||||
vperm vr10,vr6,vr5,vr16
|
||||
lvx vr4,r4,r11
|
||||
vperm vr11,vr5,vr4,vr16
|
||||
lvx vr3,r4,r12
|
||||
vperm vr12,vr4,vr3,vr16
|
||||
lvx vr2,r4,r14
|
||||
vperm vr13,vr3,vr2,vr16
|
||||
lvx vr1,r4,r15
|
||||
vperm vr14,vr2,vr1,vr16
|
||||
lvx vr0,r4,r16
|
||||
vperm vr15,vr1,vr0,vr16
|
||||
addi r4,r4,128
|
||||
stvx vr8,r0,r3
|
||||
stvx vr9,r3,r9
|
||||
stvx vr10,r3,r10
|
||||
stvx vr11,r3,r11
|
||||
stvx vr12,r3,r12
|
||||
stvx vr13,r3,r14
|
||||
stvx vr14,r3,r15
|
||||
stvx vr15,r3,r16
|
||||
addi r3,r3,128
|
||||
bdnz 8b
|
||||
|
||||
ld r14,STK_REG(r14)(r1)
|
||||
ld r15,STK_REG(r15)(r1)
|
||||
ld r16,STK_REG(r16)(r1)
|
||||
|
||||
/* Up to 127B to go */
|
||||
clrldi r5,r5,(64-7)
|
||||
srdi r6,r5,4
|
||||
mtocrf 0x01,r6
|
||||
|
||||
bf cr7*4+1,9f
|
||||
lvx vr3,r0,r4
|
||||
vperm vr8,vr0,vr3,vr16
|
||||
lvx vr2,r4,r9
|
||||
vperm vr9,vr3,vr2,vr16
|
||||
lvx vr1,r4,r10
|
||||
vperm vr10,vr2,vr1,vr16
|
||||
lvx vr0,r4,r11
|
||||
vperm vr11,vr1,vr0,vr16
|
||||
addi r4,r4,64
|
||||
stvx vr8,r0,r3
|
||||
stvx vr9,r3,r9
|
||||
stvx vr10,r3,r10
|
||||
stvx vr11,r3,r11
|
||||
addi r3,r3,64
|
||||
|
||||
9: bf cr7*4+2,10f
|
||||
lvx vr1,r0,r4
|
||||
vperm vr8,vr0,vr1,vr16
|
||||
lvx vr0,r4,r9
|
||||
vperm vr9,vr1,vr0,vr16
|
||||
addi r4,r4,32
|
||||
stvx vr8,r0,r3
|
||||
stvx vr9,r3,r9
|
||||
addi r3,r3,32
|
||||
|
||||
10: bf cr7*4+3,11f
|
||||
lvx vr1,r0,r4
|
||||
vperm vr8,vr0,vr1,vr16
|
||||
addi r4,r4,16
|
||||
stvx vr8,r0,r3
|
||||
addi r3,r3,16
|
||||
|
||||
/* Up to 15B to go */
|
||||
11: clrldi r5,r5,(64-4)
|
||||
addi r4,r4,-16 /* Unwind the +16 load offset */
|
||||
mtocrf 0x01,r5
|
||||
bf cr7*4+0,12f
|
||||
lwz r0,0(r4) /* Less chance of a reject with word ops */
|
||||
lwz r6,4(r4)
|
||||
addi r4,r4,8
|
||||
stw r0,0(r3)
|
||||
stw r6,4(r3)
|
||||
addi r3,r3,8
|
||||
|
||||
12: bf cr7*4+1,13f
|
||||
lwz r0,0(r4)
|
||||
addi r4,r4,4
|
||||
stw r0,0(r3)
|
||||
addi r3,r3,4
|
||||
|
||||
13: bf cr7*4+2,14f
|
||||
lhz r0,0(r4)
|
||||
addi r4,r4,2
|
||||
sth r0,0(r3)
|
||||
addi r3,r3,2
|
||||
|
||||
14: bf cr7*4+3,15f
|
||||
lbz r0,0(r4)
|
||||
stb r0,0(r3)
|
||||
|
||||
15: addi r1,r1,STACKFRAMESIZE
|
||||
ld r3,48(r1)
|
||||
b .exit_vmx_copy /* tail call optimise */
|
||||
#endif /* CONFiG_ALTIVEC */
|
||||
Loading…
Reference in New Issue
Block a user