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OMAP: DSS2: HDMI: change regn definition

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regn divider is currently programmed to the registers without change,
but when calculating clock frequencies it is used as regn+1.

To make this similar to how DSI handles the dividers this patch changes
the regn value to be used as such for calculations, but the value
programmed to registers is regn-1.

This simplifies the clock frequency calculations, makes it similar to
DSI, and also allows us to use regn value 0 as undefined.

Cc: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen 2011-08-22 13:16:24 +03:00
parent 8d88767a43
commit b44e45825d
3 changed files with 5 additions and 4 deletions
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6
drivers/video/omap2/dss/hdmi.c
View File

@ -60,7 +60,7 @@
#define OMAP_HDMI_TIMINGS_NB 34
#define HDMI_DEFAULT_REGN 15
#define HDMI_DEFAULT_REGN 16
#define HDMI_DEFAULT_REGM2 1
static struct {
@ -426,7 +426,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
else
pi->regn = dssdev->clocks.hdmi.regn;
refclk = clkin / (pi->regn + 1);
refclk = clkin / pi->regn;
/*
* multiplier is pixel_clk/ref_clk
@ -452,7 +452,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
* is greater than 1000MHz
*/
pi->dcofreq = phy > 1000 * 100;
pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
/* Set the reference clock to sysclk reference */
pi->refsel = HDMI_REFSEL_SYSCLK;

2
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
View File

@ -92,7 +92,7 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);

1
include/video/omapdss.h
View File

@ -520,6 +520,7 @@ struct omap_dss_device {
} dsi;
struct {
/* regn is one greater than TRM's REGN value */
u16 regn;
u16 regm2;
} hdmi;