forked from luck/tmp_suning_uos_patched
regulator: tps65217: Allow DCDC1 and DCDC3 up to 3.3V
The data sheet statement that DCDC1 and DCDC3 only can be set in the range 0.9V - 1.5V refers to storage on its internal EEPROM and therefore cold boot configuration. After power-on the device can be reconfigured over i2c and DCDC1/3 set up to 3.3V. Signed-off-by: Måns Andersson <mans.andersson@nibe.se> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -179,7 +179,8 @@ static const struct regulator_desc regulators[] = {
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TPS65217_REGULATOR("DCDC1", TPS65217_DCDC_1, "dcdc1",
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tps65217_pmic_ops, 64, TPS65217_REG_DEFDCDC1,
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TPS65217_DEFDCDCX_DCDC_MASK, TPS65217_ENABLE_DC1_EN,
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NULL, tps65217_uv1_ranges, 2, TPS65217_REG_SEQ1,
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NULL, tps65217_uv1_ranges,
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ARRAY_SIZE(tps65217_uv1_ranges), TPS65217_REG_SEQ1,
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TPS65217_SEQ1_DC1_SEQ_MASK),
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TPS65217_REGULATOR("DCDC2", TPS65217_DCDC_2, "dcdc2",
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tps65217_pmic_ops, 64, TPS65217_REG_DEFDCDC2,
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@ -190,7 +191,8 @@ static const struct regulator_desc regulators[] = {
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TPS65217_REGULATOR("DCDC3", TPS65217_DCDC_3, "dcdc3",
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tps65217_pmic_ops, 64, TPS65217_REG_DEFDCDC3,
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TPS65217_DEFDCDCX_DCDC_MASK, TPS65217_ENABLE_DC3_EN,
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NULL, tps65217_uv1_ranges, 1, TPS65217_REG_SEQ2,
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NULL, tps65217_uv1_ranges,
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ARRAY_SIZE(tps65217_uv1_ranges), TPS65217_REG_SEQ2,
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TPS65217_SEQ2_DC3_SEQ_MASK),
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TPS65217_REGULATOR("LDO1", TPS65217_LDO_1, "ldo1",
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tps65217_pmic_ldo1_ops, 16, TPS65217_REG_DEFLDO1,
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