forked from luck/tmp_suning_uos_patched
i7core_edac: Use Device 3 function 2 to report errors with RDIMM's
Nehalem and upper chipsets provide an special device that has corrected memory error counters detected with registered dimms. This device is only seen if there are registered memories plugged. After this patch, on a machine fully equiped with RDIMM's, it will use the Device 3 function 2 to count corrected errors instead on relying at mcelog. For unregistered DIMMs, it will keep the old behavior, counting errors via mcelog. This patch were developed together with Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Keith Mannthey <kmannth@us.ibm.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
61053fdedb
commit
b4e8f0b6ea
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@ -73,6 +73,18 @@
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#define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
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#define DIMM0_COR_ERR(r) ((r) & 0x7fff)
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/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
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#define MC_COR_ECC_CNT_0 0x80
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#define MC_COR_ECC_CNT_1 0x84
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#define MC_COR_ECC_CNT_2 0x88
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#define MC_COR_ECC_CNT_3 0x8c
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#define MC_COR_ECC_CNT_4 0x90
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#define MC_COR_ECC_CNT_5 0x94
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#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
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#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
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/* OFFSETS for Devices 4,5 and 6 Function 0 */
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#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
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@ -194,13 +206,20 @@ struct i7core_pvt {
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struct i7core_inject inject;
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struct i7core_channel channel[NUM_SOCKETS][NUM_CHANS];
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unsigned int is_registered:1; /* true if all memories are RDIMMs */
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int sockets; /* Number of sockets */
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int channels; /* Number of active channels */
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int ce_count_available[NUM_SOCKETS];
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/* ECC corrected errors counts per dimm */
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unsigned long ce_count[NUM_SOCKETS][MAX_DIMMS];
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int last_ce_count[NUM_SOCKETS][MAX_DIMMS];
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int csrow_map[NUM_SOCKETS][NUM_CHANS][MAX_DIMMS];
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/* ECC corrected errors counts per udimm */
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unsigned long udimm_ce_count[NUM_SOCKETS][MAX_DIMMS];
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int udimm_last_ce_count[NUM_SOCKETS][MAX_DIMMS];
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/* ECC corrected errors counts per rdimm */
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unsigned long rdimm_ce_count[NUM_SOCKETS][NUM_CHANS][MAX_DIMMS];
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int rdimm_last_ce_count[NUM_SOCKETS][NUM_CHANS][MAX_DIMMS];
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/* mcelog glue */
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struct edac_mce edac_mce;
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@ -471,6 +490,8 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
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numrow(pvt->info.max_dod >> 6),
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numcol(pvt->info.max_dod >> 9));
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pvt->is_registered = 1;
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for (i = 0; i < NUM_CHANS; i++) {
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u32 data, dimm_dod[3], value[8];
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@ -492,8 +513,14 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
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if (data & REGISTERED_DIMM)
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mtype = MEM_RDDR3;
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else
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else {
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mtype = MEM_DDR3;
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/*
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* FIXME: Currently, the driver will use dev 3:2
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* counter registers only if all memories are registered
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*/
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pvt->is_registered = 0;
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}
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#if 0
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if (data & THREE_DIMMS_PRESENT)
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pvt->channel[i].dimms = 3;
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@ -562,6 +589,8 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
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csr->channels[0].chan_idx = i;
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csr->channels[0].ce_count = 0;
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pvt->csrow_map[socket][i][j] = *csrow;
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switch (banks) {
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case 4:
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csr->dtype = DEV_X4;
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@ -1031,19 +1060,31 @@ static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
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static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
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{
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unsigned i, count, total = 0;
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unsigned i, j, count, total = 0;
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struct i7core_pvt *pvt = mci->pvt_info;
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for (i = 0; i < pvt->sockets; i++) {
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if (!pvt->ce_count_available[i])
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if (!pvt->ce_count_available[i]) {
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count = sprintf(data, "socket 0 data unavailable\n");
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else
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continue;
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}
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if (!pvt->is_registered)
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count = sprintf(data, "socket %d, dimm0: %lu\n"
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"dimm1: %lu\ndimm2: %lu\n",
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i,
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pvt->ce_count[i][0],
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pvt->ce_count[i][1],
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pvt->ce_count[i][2]);
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pvt->udimm_ce_count[i][0],
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pvt->udimm_ce_count[i][1],
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pvt->udimm_ce_count[i][2]);
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else
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for (j = 0; j < NUM_CHANS; j++) {
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count = sprintf(data, "socket %d, channel %d"
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"dimm0: %lu\n"
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"dimm1: %lu\ndimm2: %lu\n",
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i, j,
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pvt->rdimm_ce_count[i][j][0],
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pvt->rdimm_ce_count[i][j][1],
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pvt->rdimm_ce_count[i][j][2]);
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}
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data += count;
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total += count;
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}
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@ -1308,6 +1349,103 @@ static int mci_bind_devs(struct mem_ctl_info *mci)
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/****************************************************************************
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Error check routines
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****************************************************************************/
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static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci, int socket,
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int chan, int dimm, int add)
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{
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char *msg;
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struct i7core_pvt *pvt = mci->pvt_info;
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int row = pvt->csrow_map[socket][chan][dimm], i;
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for (i = 0; i < add; i++) {
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msg = kasprintf(GFP_KERNEL, "Corrected error "
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"(Socket=%d channel=%d dimm=%d",
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socket, chan, dimm);
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edac_mc_handle_fbd_ce(mci, row, 0, msg);
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kfree (msg);
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}
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}
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static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
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int socket, int chan, int new0, int new1, int new2)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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int add0 = 0, add1 = 0, add2 = 0;
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/* Updates CE counters if it is not the first time here */
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if (pvt->ce_count_available[socket]) {
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/* Updates CE counters */
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add2 = new2 - pvt->rdimm_last_ce_count[socket][chan][2];
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add1 = new1 - pvt->rdimm_last_ce_count[socket][chan][1];
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add0 = new0 - pvt->rdimm_last_ce_count[socket][chan][0];
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if (add2 < 0)
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add2 += 0x7fff;
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pvt->rdimm_ce_count[socket][chan][2] += add2;
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if (add1 < 0)
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add1 += 0x7fff;
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pvt->rdimm_ce_count[socket][chan][1] += add1;
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if (add0 < 0)
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add0 += 0x7fff;
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pvt->rdimm_ce_count[socket][chan][0] += add0;
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} else
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pvt->ce_count_available[socket] = 1;
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/* Store the new values */
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pvt->rdimm_last_ce_count[socket][chan][2] = new2;
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pvt->rdimm_last_ce_count[socket][chan][1] = new1;
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pvt->rdimm_last_ce_count[socket][chan][0] = new0;
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/*updated the edac core */
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if (add0 != 0)
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i7core_rdimm_update_csrow(mci, socket, chan, 0, add0);
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if (add1 != 0)
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i7core_rdimm_update_csrow(mci, socket, chan, 1, add1);
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if (add2 != 0)
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i7core_rdimm_update_csrow(mci, socket, chan, 2, add2);
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}
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static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci, u8 socket)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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u32 rcv[3][2];
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int i, new0, new1, new2;
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/*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
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pci_read_config_dword(pvt->pci_mcr[socket][2], MC_COR_ECC_CNT_0,
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&rcv[0][0]);
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pci_read_config_dword(pvt->pci_mcr[socket][2], MC_COR_ECC_CNT_1,
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&rcv[0][1]);
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pci_read_config_dword(pvt->pci_mcr[socket][2], MC_COR_ECC_CNT_2,
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&rcv[1][0]);
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pci_read_config_dword(pvt->pci_mcr[socket][2], MC_COR_ECC_CNT_3,
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&rcv[1][1]);
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pci_read_config_dword(pvt->pci_mcr[socket][2], MC_COR_ECC_CNT_4,
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&rcv[2][0]);
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pci_read_config_dword(pvt->pci_mcr[socket][2], MC_COR_ECC_CNT_5,
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&rcv[2][1]);
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for (i = 0 ; i < 3; i++) {
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debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
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(i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
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/*if the channel has 3 dimms*/
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if (pvt->channel[socket][i].dimms > 2) {
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new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
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new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
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new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
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} else {
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new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
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DIMM_BOT_COR_ERR(rcv[i][0]);
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new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
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DIMM_BOT_COR_ERR(rcv[i][1]);
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new2 = 0;
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}
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i7core_rdimm_update_ce_count(mci, socket, i, new0, new1, new2);
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}
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}
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/* This function is based on the device 3 function 4 registers as described on:
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* Intel Xeon Processor 5500 Series Datasheet Volume 2
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@ -1315,7 +1453,7 @@ static int mci_bind_devs(struct mem_ctl_info *mci)
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* also available at:
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* http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
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*/
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static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
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static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci, u8 socket)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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u32 rcv1, rcv0;
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@ -1326,7 +1464,7 @@ static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
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return;
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}
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/* Corrected error reads */
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/* Corrected test errors */
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pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV1, &rcv1);
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pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV0, &rcv0);
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@ -1335,39 +1473,38 @@ static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
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new1 = DIMM1_COR_ERR(rcv0);
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new0 = DIMM0_COR_ERR(rcv0);
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#if 0
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debugf2("%s CE rcv1=0x%08x rcv0=0x%08x, %d %d %d\n",
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(pvt->ce_count_available ? "UPDATE" : "READ"),
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rcv1, rcv0, new0, new1, new2);
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#endif
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/* Updates CE counters if it is not the first time here */
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if (pvt->ce_count_available[socket]) {
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/* Updates CE counters */
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int add0, add1, add2;
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add2 = new2 - pvt->last_ce_count[socket][2];
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add1 = new1 - pvt->last_ce_count[socket][1];
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add0 = new0 - pvt->last_ce_count[socket][0];
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add2 = new2 - pvt->udimm_last_ce_count[socket][2];
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add1 = new1 - pvt->udimm_last_ce_count[socket][1];
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add0 = new0 - pvt->udimm_last_ce_count[socket][0];
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if (add2 < 0)
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add2 += 0x7fff;
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pvt->ce_count[socket][2] += add2;
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pvt->udimm_ce_count[socket][2] += add2;
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if (add1 < 0)
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add1 += 0x7fff;
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pvt->ce_count[socket][1] += add1;
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pvt->udimm_ce_count[socket][1] += add1;
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if (add0 < 0)
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add0 += 0x7fff;
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pvt->ce_count[socket][0] += add0;
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pvt->udimm_ce_count[socket][0] += add0;
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if (add0 | add1 | add2)
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i7core_printk(KERN_ERR, "New Corrected error(s): "
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"dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
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add0, add1, add2);
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} else
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pvt->ce_count_available[socket] = 1;
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/* Store the new values */
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pvt->last_ce_count[socket][2] = new2;
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pvt->last_ce_count[socket][1] = new1;
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pvt->last_ce_count[socket][0] = new0;
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pvt->udimm_last_ce_count[socket][2] = new2;
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pvt->udimm_last_ce_count[socket][1] = new1;
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pvt->udimm_last_ce_count[socket][0] = new0;
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}
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/*
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@ -1386,6 +1523,7 @@ static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
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static void i7core_mce_output_error(struct mem_ctl_info *mci,
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struct mce *m)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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char *type, *optype, *err, *msg;
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unsigned long error = m->status & 0x1ff0000l;
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u32 optypenum = (m->status >> 4) & 0x07;
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@ -1394,6 +1532,7 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
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u32 channel = (m->misc >> 18) & 0x3;
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u32 syndrome = m->misc >> 32;
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u32 errnum = find_first_bit(&error, 32);
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int csrow;
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if (m->mcgstatus & 1)
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type = "FATAL";
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@ -1463,9 +1602,15 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
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debugf0("%s", msg);
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csrow = pvt->csrow_map[m->cpu][channel][dimm];
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/* Call the helper to output message */
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edac_mc_handle_fbd_ue(mci, 0 /* FIXME: should be rank here */,
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0, 0 /* FIXME: should be channel here */, msg);
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if (m->mcgstatus & 1)
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edac_mc_handle_fbd_ue(mci, csrow, 0,
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0 /* FIXME: should be channel here */, msg);
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else if (!pvt->is_registered)
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edac_mc_handle_fbd_ce(mci, csrow,
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0 /* FIXME: should be channel here */, msg);
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kfree(msg);
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}
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@ -1502,7 +1647,10 @@ static void i7core_check_error(struct mem_ctl_info *mci)
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/* check memory count errors */
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for (i = 0; i < pvt->sockets; i++)
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check_mc_test_err(mci, i);
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if (!pvt->is_registered)
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i7core_udimm_check_mc_ecc_err(mci, i);
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else
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i7core_rdimm_check_mc_ecc_err(mci, i);
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}
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/*
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