forked from luck/tmp_suning_uos_patched
[IA64] Fix race in mm-context wrap-around logic.
The patch below should fix a race which could cause stale TLB entries. Specifically, when 2 CPUs ended up racing for entrance to wrap_mmu_context(). The losing CPU would find that by the time it acquired ctx.lock, mm->context already had a valid value, but then it failed to (re-)check the delayed TLB flushing logic and hence could end up using a context number when there were still stale entries in its TLB. The fix is to check for delayed TLB flushes only after mm->context is valid (non-zero). The patch also makes GCC v4.x happier by defining a non-volatile variant of mm_context_t called nv_mm_context_t. Signed-off-by: David Mosberger-Tang <David.Mosberger@acm.org> Signed-off-by: Tony Luck <tony.luck@intel.com>
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@ -2,10 +2,12 @@
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#define __MMU_H
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/*
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* Type for a context number. We declare it volatile to ensure proper ordering when it's
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* accessed outside of spinlock'd critical sections (e.g., as done in activate_mm() and
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* init_new_context()).
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* Type for a context number. We declare it volatile to ensure proper
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* ordering when it's accessed outside of spinlock'd critical sections
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* (e.g., as done in activate_mm() and init_new_context()).
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*/
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typedef volatile unsigned long mm_context_t;
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typedef unsigned long nv_mm_context_t;
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#endif
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@ -55,34 +55,46 @@ static inline void
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delayed_tlb_flush (void)
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{
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extern void local_flush_tlb_all (void);
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unsigned long flags;
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if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
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local_flush_tlb_all();
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__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
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spin_lock_irqsave(&ia64_ctx.lock, flags);
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{
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if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
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local_flush_tlb_all();
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__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
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}
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}
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spin_unlock_irqrestore(&ia64_ctx.lock, flags);
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}
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}
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static inline mm_context_t
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static inline nv_mm_context_t
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get_mmu_context (struct mm_struct *mm)
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{
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unsigned long flags;
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mm_context_t context = mm->context;
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nv_mm_context_t context = mm->context;
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if (context)
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return context;
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spin_lock_irqsave(&ia64_ctx.lock, flags);
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{
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/* re-check, now that we've got the lock: */
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context = mm->context;
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if (context == 0) {
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cpus_clear(mm->cpu_vm_mask);
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if (ia64_ctx.next >= ia64_ctx.limit)
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wrap_mmu_context(mm);
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mm->context = context = ia64_ctx.next++;
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if (unlikely(!context)) {
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spin_lock_irqsave(&ia64_ctx.lock, flags);
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{
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/* re-check, now that we've got the lock: */
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context = mm->context;
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if (context == 0) {
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cpus_clear(mm->cpu_vm_mask);
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if (ia64_ctx.next >= ia64_ctx.limit)
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wrap_mmu_context(mm);
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mm->context = context = ia64_ctx.next++;
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}
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}
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spin_unlock_irqrestore(&ia64_ctx.lock, flags);
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}
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spin_unlock_irqrestore(&ia64_ctx.lock, flags);
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/*
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* Ensure we're not starting to use "context" before any old
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* uses of it are gone from our TLB.
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*/
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delayed_tlb_flush();
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return context;
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}
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@ -104,7 +116,7 @@ destroy_context (struct mm_struct *mm)
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}
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static inline void
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reload_context (mm_context_t context)
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reload_context (nv_mm_context_t context)
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{
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unsigned long rid;
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unsigned long rid_incr = 0;
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@ -138,7 +150,7 @@ reload_context (mm_context_t context)
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static inline void
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activate_context (struct mm_struct *mm)
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{
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mm_context_t context;
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nv_mm_context_t context;
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do {
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context = get_mmu_context(mm);
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@ -157,8 +169,6 @@ activate_context (struct mm_struct *mm)
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static inline void
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activate_mm (struct mm_struct *prev, struct mm_struct *next)
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{
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delayed_tlb_flush();
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/*
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* We may get interrupts here, but that's OK because interrupt handlers cannot
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* touch user-space.
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