forked from luck/tmp_suning_uos_patched
sh: Split out MMUCR.URB based entry wiring in to shared helper.
Presently this is duplicated between tlb-sh4 and tlb-pteaex. Split the helpers out in to a generic tlb-urb that can be used by any parts equipped with MMUCR.URB. At the same time, move the SH-5 code out-of-line, as we require single global state for DTLB entry wiring. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
046581f962
commit
bb29c677b3
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@ -98,49 +98,9 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
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#define tlb_migrate_finish(mm) do { } while (0)
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#ifdef CONFIG_CPU_SH4
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#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SUPERH64)
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extern void tlb_wire_entry(struct vm_area_struct *, unsigned long, pte_t);
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extern void tlb_unwire_entry(void);
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#elif defined(CONFIG_SUPERH64)
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static int dtlb_entry;
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static unsigned long long dtlb_entries[64];
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static inline void tlb_wire_entry(struct vm_area_struct *vma,
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unsigned long addr, pte_t pte)
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{
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unsigned long long entry;
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unsigned long paddr, flags;
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BUG_ON(dtlb_entry == 64);
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local_irq_save(flags);
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entry = sh64_get_wired_dtlb_entry();
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dtlb_entries[dtlb_entry++] = entry;
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paddr = pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK;
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paddr &= ~PAGE_MASK;
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sh64_setup_tlb_slot(entry, addr, get_asid(), paddr);
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local_irq_restore(flags);
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}
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static inline void tlb_unwire_entry(void)
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{
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unsigned long long entry;
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unsigned long flags;
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BUG_ON(!dtlb_entry);
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local_irq_save(flags);
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entry = dtlb_entries[dtlb_entry--];
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sh64_teardown_tlb_slot(entry);
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sh64_put_wired_dtlb_entry(entry);
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local_irq_restore(flags);
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}
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#else
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static inline void tlb_wire_entry(struct vm_area_struct *vma ,
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unsigned long addr, pte_t pte)
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@ -152,7 +112,7 @@ static inline void tlb_unwire_entry(void)
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{
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BUG();
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}
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#endif /* CONFIG_CPU_SH4 */
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#endif
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#else /* CONFIG_MMU */
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@ -26,9 +26,9 @@ endif
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ifdef CONFIG_MMU
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tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o
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tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o
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tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o tlb-urb.o
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tlb-$(CONFIG_CPU_SH5) := tlb-sh5.o
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tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o
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tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o tlb-urb.o
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obj-y += $(tlb-y)
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endif
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@ -76,69 +76,3 @@ void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
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__raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
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back_to_cached();
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}
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/*
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* Load the entry for 'addr' into the TLB and wire the entry.
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*/
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void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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{
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unsigned long status, flags;
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int urb;
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local_irq_save(flags);
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/* Load the entry into the TLB */
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__update_tlb(vma, addr, pte);
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/* ... and wire it up. */
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status = ctrl_inl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URB;
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/*
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* Make sure we're not trying to wire the last TLB entry slot.
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*/
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BUG_ON(!--urb);
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urb = urb % MMUCR_URB_NENTRIES;
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status |= (urb << MMUCR_URB_SHIFT);
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ctrl_outl(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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/*
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* Unwire the last wired TLB entry.
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*
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* It should also be noted that it is not possible to wire and unwire
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* TLB entries in an arbitrary order. If you wire TLB entry N, followed
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* by entry N+1, you must unwire entry N+1 first, then entry N. In this
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* respect, it works like a stack or LIFO queue.
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*/
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void tlb_unwire_entry(void)
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{
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unsigned long status, flags;
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int urb;
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local_irq_save(flags);
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status = ctrl_inl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URB;
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/*
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* Make sure we're not trying to unwire a TLB entry when none
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* have been wired.
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*/
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BUG_ON(urb++ == MMUCR_URB_NENTRIES);
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urb = urb % MMUCR_URB_NENTRIES;
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status |= (urb << MMUCR_URB_SHIFT);
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ctrl_outl(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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@ -81,69 +81,3 @@ void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
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ctrl_outl(data, addr);
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back_to_cached();
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}
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/*
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* Load the entry for 'addr' into the TLB and wire the entry.
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*/
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void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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{
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unsigned long status, flags;
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int urb;
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local_irq_save(flags);
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/* Load the entry into the TLB */
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__update_tlb(vma, addr, pte);
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/* ... and wire it up. */
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status = ctrl_inl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URB;
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/*
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* Make sure we're not trying to wire the last TLB entry slot.
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*/
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BUG_ON(!--urb);
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urb = urb % MMUCR_URB_NENTRIES;
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status |= (urb << MMUCR_URB_SHIFT);
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ctrl_outl(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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/*
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* Unwire the last wired TLB entry.
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*
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* It should also be noted that it is not possible to wire and unwire
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* TLB entries in an arbitrary order. If you wire TLB entry N, followed
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* by entry N+1, you must unwire entry N+1 first, then entry N. In this
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* respect, it works like a stack or LIFO queue.
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*/
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void tlb_unwire_entry(void)
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{
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unsigned long status, flags;
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int urb;
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local_irq_save(flags);
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status = ctrl_inl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URB;
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/*
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* Make sure we're not trying to unwire a TLB entry when none
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* have been wired.
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*/
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BUG_ON(urb++ == MMUCR_URB_NENTRIES);
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urb = urb % MMUCR_URB_NENTRIES;
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status |= (urb << MMUCR_URB_SHIFT);
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ctrl_outl(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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@ -143,3 +143,42 @@ void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
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*/
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void sh64_teardown_tlb_slot(unsigned long long config_addr)
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__attribute__ ((alias("__flush_tlb_slot")));
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static int dtlb_entry;
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static unsigned long long dtlb_entries[64];
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void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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{
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unsigned long long entry;
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unsigned long paddr, flags;
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BUG_ON(dtlb_entry == ARRAY_SIZE(dtlb_entries));
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local_irq_save(flags);
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entry = sh64_get_wired_dtlb_entry();
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dtlb_entries[dtlb_entry++] = entry;
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paddr = pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK;
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paddr &= ~PAGE_MASK;
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sh64_setup_tlb_slot(entry, addr, get_asid(), paddr);
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local_irq_restore(flags);
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}
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void tlb_unwire_entry(void)
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{
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unsigned long long entry;
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unsigned long flags;
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BUG_ON(!dtlb_entry);
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local_irq_save(flags);
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entry = dtlb_entries[dtlb_entry--];
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sh64_teardown_tlb_slot(entry);
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sh64_put_wired_dtlb_entry(entry);
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local_irq_restore(flags);
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}
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81
arch/sh/mm/tlb-urb.c
Normal file
81
arch/sh/mm/tlb-urb.c
Normal file
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@ -0,0 +1,81 @@
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/*
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* arch/sh/mm/tlb-urb.c
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*
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* TLB entry wiring helpers for URB-equipped parts.
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*
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* Copyright (C) 2010 Matt Fleming
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <asm/tlb.h>
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#include <asm/mmu_context.h>
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/*
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* Load the entry for 'addr' into the TLB and wire the entry.
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*/
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void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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{
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unsigned long status, flags;
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int urb;
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local_irq_save(flags);
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/* Load the entry into the TLB */
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__update_tlb(vma, addr, pte);
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/* ... and wire it up. */
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status = __raw_readl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URB;
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/*
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* Make sure we're not trying to wire the last TLB entry slot.
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*/
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BUG_ON(!--urb);
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urb = urb % MMUCR_URB_NENTRIES;
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status |= (urb << MMUCR_URB_SHIFT);
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__raw_writel(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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/*
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* Unwire the last wired TLB entry.
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*
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* It should also be noted that it is not possible to wire and unwire
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* TLB entries in an arbitrary order. If you wire TLB entry N, followed
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* by entry N+1, you must unwire entry N+1 first, then entry N. In this
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* respect, it works like a stack or LIFO queue.
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*/
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void tlb_unwire_entry(void)
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{
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unsigned long status, flags;
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int urb;
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local_irq_save(flags);
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status = __raw_readl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URB;
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/*
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* Make sure we're not trying to unwire a TLB entry when none
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* have been wired.
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*/
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BUG_ON(urb++ == MMUCR_URB_NENTRIES);
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urb = urb % MMUCR_URB_NENTRIES;
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status |= (urb << MMUCR_URB_SHIFT);
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__raw_writel(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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