forked from luck/tmp_suning_uos_patched
at_hdmac: move to generic DMA binding
Update at_hdmac driver to support generic DMA device tree binding. Devices can still request channel with dma_request_channel() then it doesn't break DMA for non DT boards. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Ludovic Desroches
Vinod Koul
parent
e6a30fec08
commit
bbe89c8e3d
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@ -1,14 +1,39 @@
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* Atmel Direct Memory Access Controller (DMA)
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Required properties:
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- compatible: Should be "atmel,<chip>-dma"
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- reg: Should contain DMA registers location and length
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- interrupts: Should contain DMA interrupt
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- compatible: Should be "atmel,<chip>-dma".
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- reg: Should contain DMA registers location and length.
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- interrupts: Should contain DMA interrupt.
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- #dma-cells: Must be <2>, used to represent the number of integer cells in
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the dmas property of client devices.
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Examples:
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Example:
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dma@ffffec00 {
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dma0: dma@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <21>;
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#dma-cells = <2>;
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};
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DMA clients connected to the Atmel DMA controller must use the format
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described in the dma.txt file, using a three-cell specifier for each channel:
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a phandle plus two interger cells.
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The three cells in order are:
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1. A phandle pointing to the DMA controller.
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2. The memory interface (16 most significant bits), the peripheral interface
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(16 less significant bits).
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3. The peripheral identifier for the hardware handshaking interface. The
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identifier can be different for tx and rx.
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Example:
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i2c0@i2c@f8010000 {
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compatible = "atmel,at91sam9x5-i2c";
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reg = <0xf8010000 0x100>;
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interrupts = <9 4 6>;
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dmas = <&dma0 1 7>,
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<&dma0 1 8>;
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dma-names = "tx", "rx";
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};
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@ -24,6 +24,7 @@
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include "at_hdmac_regs.h"
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#include "dmaengine.h"
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@ -676,7 +677,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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ctrlb |= ATC_DST_ADDR_MODE_FIXED
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| ATC_SRC_ADDR_MODE_INCR
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| ATC_FC_MEM2PER
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| ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF);
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| ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if);
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reg = sconfig->dst_addr;
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for_each_sg(sgl, sg, sg_len, i) {
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struct at_desc *desc;
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@ -715,7 +716,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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ctrlb |= ATC_DST_ADDR_MODE_INCR
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| ATC_SRC_ADDR_MODE_FIXED
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| ATC_FC_PER2MEM
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| ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF);
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| ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if);
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reg = sconfig->src_addr;
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for_each_sg(sgl, sg, sg_len, i) {
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@ -821,8 +822,8 @@ atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
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desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
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| ATC_SRC_ADDR_MODE_INCR
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| ATC_FC_MEM2PER
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| ATC_SIF(AT_DMA_MEM_IF)
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| ATC_DIF(AT_DMA_PER_IF);
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| ATC_SIF(atchan->mem_if)
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| ATC_DIF(atchan->per_if);
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break;
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case DMA_DEV_TO_MEM:
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@ -832,8 +833,8 @@ atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
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desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
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| ATC_SRC_ADDR_MODE_FIXED
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| ATC_FC_PER2MEM
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| ATC_SIF(AT_DMA_PER_IF)
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| ATC_DIF(AT_DMA_MEM_IF);
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| ATC_SIF(atchan->per_if)
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| ATC_DIF(atchan->mem_if);
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break;
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default:
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@ -1189,6 +1190,67 @@ static void atc_free_chan_resources(struct dma_chan *chan)
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dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
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}
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#ifdef CONFIG_OF
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static bool at_dma_filter(struct dma_chan *chan, void *slave)
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{
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struct at_dma_slave *atslave = slave;
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if (atslave->dma_dev == chan->device->dev) {
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chan->private = atslave;
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return true;
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} else {
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return false;
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}
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}
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static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
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struct of_dma *of_dma)
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{
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struct dma_chan *chan;
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struct at_dma_chan *atchan;
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struct at_dma_slave *atslave;
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dma_cap_mask_t mask;
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unsigned int per_id;
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struct platform_device *dmac_pdev;
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if (dma_spec->args_count != 2)
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return NULL;
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dmac_pdev = of_find_device_by_node(dma_spec->np);
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL);
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if (!atslave)
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return NULL;
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/*
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* We can fill both SRC_PER and DST_PER, one of these fields will be
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* ignored depending on DMA transfer direction.
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*/
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per_id = dma_spec->args[1];
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atslave->cfg = ATC_FIFOCFG_HALFFIFO | ATC_DST_H2SEL_HW
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| ATC_SRC_H2SEL_HW | ATC_DST_PER(per_id)
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| ATC_SRC_PER(per_id);
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atslave->dma_dev = &dmac_pdev->dev;
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chan = dma_request_channel(mask, at_dma_filter, atslave);
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if (!chan)
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return NULL;
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atchan = to_at_dma_chan(chan);
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atchan->per_if = dma_spec->args[0] & 0xff;
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atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff;
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return chan;
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}
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#else
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static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
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struct of_dma *of_dma)
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{
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return NULL;
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}
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#endif
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/*-- Module Management -----------------------------------------------*/
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@ -1343,6 +1405,8 @@ static int __init at_dma_probe(struct platform_device *pdev)
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for (i = 0; i < plat_dat->nr_channels; i++) {
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struct at_dma_chan *atchan = &atdma->chan[i];
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atchan->mem_if = AT_DMA_MEM_IF;
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atchan->per_if = AT_DMA_PER_IF;
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atchan->chan_common.device = &atdma->dma_common;
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dma_cookie_init(&atchan->chan_common);
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list_add_tail(&atchan->chan_common.device_node,
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@ -1389,8 +1453,25 @@ static int __init at_dma_probe(struct platform_device *pdev)
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dma_async_device_register(&atdma->dma_common);
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/*
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* Do not return an error if the dmac node is not present in order to
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* not break the existing way of requesting channel with
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* dma_request_channel().
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*/
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if (pdev->dev.of_node) {
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err = of_dma_controller_register(pdev->dev.of_node,
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at_dma_xlate, atdma);
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if (err) {
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dev_err(&pdev->dev, "could not register of_dma_controller\n");
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goto err_of_dma_controller_register;
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}
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}
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return 0;
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err_of_dma_controller_register:
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dma_async_device_unregister(&atdma->dma_common);
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dma_pool_destroy(atdma->dma_desc_pool);
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err_pool_create:
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platform_set_drvdata(pdev, NULL);
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free_irq(platform_get_irq(pdev, 0), atdma);
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@ -220,6 +220,8 @@ enum atc_status {
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* @device: parent device
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* @ch_regs: memory mapped register base
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* @mask: channel index in a mask
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* @per_if: peripheral interface
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* @mem_if: memory interface
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* @status: transmit status information from irq/prep* functions
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* to tasklet (use atomic operations)
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* @tasklet: bottom half to finish transaction work
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@ -238,6 +240,8 @@ struct at_dma_chan {
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struct at_dma *device;
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void __iomem *ch_regs;
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u8 mask;
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u8 per_if;
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u8 mem_if;
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unsigned long status;
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struct tasklet_struct tasklet;
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u32 save_cfg;
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