forked from luck/tmp_suning_uos_patched
V4L/DVB (6856): zl10353: improve tuning parameters and update register map
Some more I2C traces and a experimentation with register values on both the ZL10353 and MT352 mean that I can now guess at what more of the ZL10353 registers do. Guess at the registers' names (based on the equivalent names in MT352) and update set_parameters/get_parameters with the new knowledge. Signed-off-by: Chris Pascoe <c.pascoe@itee.uq.edu.au> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Chris Pascoe
Mauro Carvalho Chehab
parent
3dfefc50ff
commit
bc51471088
@ -36,6 +36,8 @@ struct zl10353_state {
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struct dvb_frontend frontend;
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struct zl10353_config config;
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enum fe_bandwidth bandwidth;
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};
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static int debug;
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@ -195,27 +197,156 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
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{
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struct zl10353_state *state = fe->demodulator_priv;
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u16 nominal_rate, input_freq;
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u8 pllbuf[6] = { 0x67 };
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u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
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u16 tps = 0;
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struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
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/* These settings set "auto-everything" and start the FSM. */
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zl10353_single_write(fe, 0x55, 0x80);
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zl10353_single_write(fe, RESET, 0x80);
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udelay(200);
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zl10353_single_write(fe, 0xEA, 0x01);
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udelay(200);
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zl10353_single_write(fe, 0xEA, 0x00);
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zl10353_single_write(fe, 0x56, 0x28);
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zl10353_single_write(fe, 0x89, 0x20);
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zl10353_single_write(fe, 0x5E, 0x00);
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zl10353_single_write(fe, AGC_TARGET, 0x28);
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zl10353_calc_nominal_rate(fe, param->u.ofdm.bandwidth, &nominal_rate);
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if (op->transmission_mode != TRANSMISSION_MODE_AUTO)
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acq_ctl |= (1 << 0);
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if (op->guard_interval != GUARD_INTERVAL_AUTO)
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acq_ctl |= (1 << 1);
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zl10353_single_write(fe, ACQ_CTL, acq_ctl);
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switch (op->bandwidth) {
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case BANDWIDTH_6_MHZ:
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/* These are extrapolated from the 7 and 8MHz values */
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zl10353_single_write(fe, MCLK_RATIO, 0x97);
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zl10353_single_write(fe, 0x64, 0x34);
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break;
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case BANDWIDTH_7_MHZ:
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zl10353_single_write(fe, MCLK_RATIO, 0x86);
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zl10353_single_write(fe, 0x64, 0x35);
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break;
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case BANDWIDTH_8_MHZ:
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default:
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zl10353_single_write(fe, MCLK_RATIO, 0x75);
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zl10353_single_write(fe, 0x64, 0x36);
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}
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zl10353_calc_nominal_rate(fe, op->bandwidth, &nominal_rate);
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zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
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zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
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state->bandwidth = op->bandwidth;
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zl10353_calc_input_freq(fe, &input_freq);
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zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
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zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));
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/* Hint at TPS settings */
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switch (op->code_rate_HP) {
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case FEC_2_3:
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tps |= (1 << 7);
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break;
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case FEC_3_4:
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tps |= (2 << 7);
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break;
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case FEC_5_6:
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tps |= (3 << 7);
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break;
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case FEC_7_8:
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tps |= (4 << 7);
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break;
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case FEC_1_2:
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case FEC_AUTO:
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break;
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default:
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return -EINVAL;
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}
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switch (op->code_rate_LP) {
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case FEC_2_3:
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tps |= (1 << 4);
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break;
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case FEC_3_4:
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tps |= (2 << 4);
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break;
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case FEC_5_6:
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tps |= (3 << 4);
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break;
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case FEC_7_8:
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tps |= (4 << 4);
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break;
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case FEC_1_2:
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case FEC_AUTO:
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break;
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case FEC_NONE:
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if (op->hierarchy_information == HIERARCHY_AUTO ||
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op->hierarchy_information == HIERARCHY_NONE)
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break;
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default:
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return -EINVAL;
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}
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switch (op->constellation) {
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case QPSK:
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break;
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case QAM_AUTO:
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case QAM_16:
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tps |= (1 << 13);
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break;
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case QAM_64:
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tps |= (2 << 13);
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break;
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default:
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return -EINVAL;
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}
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switch (op->transmission_mode) {
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case TRANSMISSION_MODE_2K:
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case TRANSMISSION_MODE_AUTO:
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break;
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case TRANSMISSION_MODE_8K:
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tps |= (1 << 0);
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break;
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default:
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return -EINVAL;
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}
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switch (op->guard_interval) {
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case GUARD_INTERVAL_1_32:
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case GUARD_INTERVAL_AUTO:
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break;
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case GUARD_INTERVAL_1_16:
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tps |= (1 << 2);
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break;
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case GUARD_INTERVAL_1_8:
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tps |= (2 << 2);
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break;
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case GUARD_INTERVAL_1_4:
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tps |= (3 << 2);
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break;
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default:
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return -EINVAL;
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}
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switch (op->hierarchy_information) {
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case HIERARCHY_AUTO:
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case HIERARCHY_NONE:
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break;
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case HIERARCHY_1:
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tps |= (1 << 10);
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break;
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case HIERARCHY_2:
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tps |= (2 << 10);
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break;
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case HIERARCHY_4:
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tps |= (3 << 10);
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break;
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default:
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return -EINVAL;
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}
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zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
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zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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@ -244,12 +375,97 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
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else
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zl10353_single_write(fe, TUNER_GO, 0x01);
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udelay(250);
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zl10353_single_write(fe, 0xE4, 0x00);
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zl10353_single_write(fe, 0xE5, 0x2A);
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zl10353_single_write(fe, 0xE9, 0x02);
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zl10353_single_write(fe, 0xE7, 0x40);
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zl10353_single_write(fe, 0xE8, 0x10);
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return 0;
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}
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static int zl10353_get_parameters(struct dvb_frontend *fe,
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struct dvb_frontend_parameters *param)
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{
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struct zl10353_state *state = fe->demodulator_priv;
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struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
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int s6, s9;
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u16 tps;
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static const u8 tps_fec_to_api[8] = {
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FEC_1_2,
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FEC_2_3,
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FEC_3_4,
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FEC_5_6,
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FEC_7_8,
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FEC_AUTO,
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FEC_AUTO,
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FEC_AUTO
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};
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s6 = zl10353_read_register(state, STATUS_6);
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s9 = zl10353_read_register(state, STATUS_9);
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if (s6 < 0 || s9 < 0)
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return -EREMOTEIO;
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if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0)
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return -EINVAL; /* no FE or TPS lock */
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tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 |
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zl10353_read_register(state, TPS_RECEIVED_0);
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op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
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op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
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switch ((tps >> 13) & 3) {
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case 0:
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op->constellation = QPSK;
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break;
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case 1:
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op->constellation = QAM_16;
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break;
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case 2:
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op->constellation = QAM_64;
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break;
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default:
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op->constellation = QAM_AUTO;
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break;
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}
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op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
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TRANSMISSION_MODE_2K;
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switch ((tps >> 2) & 3) {
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case 0:
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op->guard_interval = GUARD_INTERVAL_1_32;
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break;
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case 1:
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op->guard_interval = GUARD_INTERVAL_1_16;
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break;
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case 2:
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op->guard_interval = GUARD_INTERVAL_1_8;
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break;
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case 3:
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op->guard_interval = GUARD_INTERVAL_1_4;
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break;
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default:
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op->guard_interval = GUARD_INTERVAL_AUTO;
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break;
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}
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switch ((tps >> 10) & 7) {
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case 0:
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op->hierarchy_information = HIERARCHY_NONE;
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break;
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case 1:
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op->hierarchy_information = HIERARCHY_1;
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break;
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case 2:
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op->hierarchy_information = HIERARCHY_2;
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break;
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case 3:
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op->hierarchy_information = HIERARCHY_4;
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break;
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default:
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op->hierarchy_information = HIERARCHY_AUTO;
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break;
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}
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param->frequency = 0;
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op->bandwidth = state->bandwidth;
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param->inversion = INVERSION_AUTO;
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return 0;
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}
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@ -438,6 +654,7 @@ static struct dvb_frontend_ops zl10353_ops = {
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.write = zl10353_write,
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.set_frontend = zl10353_set_parameters,
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.get_frontend = zl10353_get_parameters,
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.get_tune_settings = zl10353_get_tune_settings,
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.read_status = zl10353_read_status,
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@ -46,13 +46,28 @@ enum zl10353_reg_addr {
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RS_ERR_CNT_0 = 0x13,
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RS_UBC_1 = 0x14,
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RS_UBC_0 = 0x15,
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TPS_RECEIVED_1 = 0x1D,
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TPS_RECEIVED_0 = 0x1E,
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TPS_CURRENT_1 = 0x1F,
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TPS_CURRENT_0 = 0x20,
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RESET = 0x55,
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AGC_TARGET = 0x56,
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MCLK_RATIO = 0x5C,
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ACQ_CTL = 0x5E,
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TRL_NOMINAL_RATE_1 = 0x65,
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TRL_NOMINAL_RATE_0 = 0x66,
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INPUT_FREQ_1 = 0x6C,
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INPUT_FREQ_0 = 0x6D,
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TPS_GIVEN_1 = 0x6E,
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TPS_GIVEN_0 = 0x6F,
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TUNER_GO = 0x70,
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FSM_GO = 0x71,
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CHIP_ID = 0x7F,
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CHAN_STEP_1 = 0xE4,
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CHAN_STEP_0 = 0xE5,
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OFDM_LOCK_TIME = 0xE7,
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FEC_LOCK_TIME = 0xE8,
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ACQ_DELAY = 0xE9,
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};
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#endif /* _ZL10353_PRIV_ */
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