forked from luck/tmp_suning_uos_patched
drivers/rtc/rtc-m41t93.c: don't let get_time() reset M41T93_FLAG_OF
If the rtc reports the time might be invalid due to oscillator failure, M41T93_FLAG_OF flag must not be reset by get_time() as the read operation doesn't make the time valid. Without this patch, only the first get_time() reported an invalid time, the second get_time() reported a valid time althought the reported time is probably wrong due to oscillator failure. Instead of resetting in get_time(), with this patch M41T93_FLAG_OF is reset in set_time() when a valid time is to be written. Signed-off-by: Nikolaus Voss <n.voss@weinmann.de> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -48,6 +48,7 @@ static inline int m41t93_set_reg(struct spi_device *spi, u8 addr, u8 data)
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static int m41t93_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct spi_device *spi = to_spi_device(dev);
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int tmp;
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u8 buf[9] = {0x80}; /* write cmd + 8 data bytes */
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u8 * const data = &buf[1]; /* ptr to first data byte */
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@ -62,6 +63,30 @@ static int m41t93_set_time(struct device *dev, struct rtc_time *tm)
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return -EINVAL;
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}
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tmp = spi_w8r8(spi, M41T93_REG_FLAGS);
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if (tmp < 0)
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return tmp;
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if (tmp & M41T93_FLAG_OF) {
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dev_warn(&spi->dev, "OF bit is set, resetting.\n");
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m41t93_set_reg(spi, M41T93_REG_FLAGS, tmp & ~M41T93_FLAG_OF);
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tmp = spi_w8r8(spi, M41T93_REG_FLAGS);
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if (tmp < 0) {
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return tmp;
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} else if (tmp & M41T93_FLAG_OF) {
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/* OF cannot be immediately reset: oscillator has to be
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* restarted. */
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u8 reset_osc = buf[M41T93_REG_ST_SEC] | M41T93_FLAG_ST;
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dev_warn(&spi->dev,
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"OF bit is still set, kickstarting clock.\n");
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m41t93_set_reg(spi, M41T93_REG_ST_SEC, reset_osc);
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reset_osc &= ~M41T93_FLAG_ST;
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m41t93_set_reg(spi, M41T93_REG_ST_SEC, reset_osc);
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}
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}
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data[M41T93_REG_SSEC] = 0;
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data[M41T93_REG_ST_SEC] = bin2bcd(tm->tm_sec);
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data[M41T93_REG_MIN] = bin2bcd(tm->tm_min);
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@ -89,10 +114,7 @@ static int m41t93_get_time(struct device *dev, struct rtc_time *tm)
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1. halt bit (HT) is set: the clock is running but update of readout
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registers has been disabled due to power failure. This is normal
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case after poweron. Time is valid after resetting HT bit.
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2. oscillator fail bit (OF) is set. Oscillator has be stopped and
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time is invalid:
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a) OF can be immeditely reset.
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b) OF cannot be immediately reset: oscillator has to be restarted.
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2. oscillator fail bit (OF) is set: time is invalid.
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*/
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tmp = spi_w8r8(spi, M41T93_REG_ALM_HOUR_HT);
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if (tmp < 0)
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@ -110,21 +132,7 @@ static int m41t93_get_time(struct device *dev, struct rtc_time *tm)
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if (tmp & M41T93_FLAG_OF) {
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ret = -EINVAL;
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dev_warn(&spi->dev, "OF bit is set, resetting.\n");
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m41t93_set_reg(spi, M41T93_REG_FLAGS, tmp & ~M41T93_FLAG_OF);
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tmp = spi_w8r8(spi, M41T93_REG_FLAGS);
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if (tmp < 0)
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return tmp;
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else if (tmp & M41T93_FLAG_OF) {
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u8 reset_osc = buf[M41T93_REG_ST_SEC] | M41T93_FLAG_ST;
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dev_warn(&spi->dev,
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"OF bit is still set, kickstarting clock.\n");
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m41t93_set_reg(spi, M41T93_REG_ST_SEC, reset_osc);
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reset_osc &= ~M41T93_FLAG_ST;
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m41t93_set_reg(spi, M41T93_REG_ST_SEC, reset_osc);
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}
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dev_warn(&spi->dev, "OF bit is set, write time to restart.\n");
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}
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if (tmp & M41T93_FLAG_BL)
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