forked from luck/tmp_suning_uos_patched
scsi: esp_scsi: Add support for FSC chip
The FSC (NCR53CF9x-2 / SYM53CF9x-2) has a different family code than QLogic or Emulex parts. This caused it to be detected as a FAS100A. Unforunately, this meant the configuration of the CONFIG3 register was incorrect. This causes data transfer issues with FAST-SCSI targets. The FSC also has the CONFIG4 register. It can be used to enable a feature called Active Negation which should always be enabled according to the data manual. Link: https://lore.kernel.org/r/20191119202021.28720-3-jongk@linux-m68k.org Reviewed-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: Kars de Jong <jongk@linux-m68k.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -243,8 +243,6 @@ static void esp_set_all_config3(struct esp *esp, u8 val)
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/* Reset the ESP chip, _not_ the SCSI bus. */
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static void esp_reset_esp(struct esp *esp)
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{
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u8 family_code, version;
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/* Now reset the ESP chip */
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scsi_esp_cmd(esp, ESP_CMD_RC);
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scsi_esp_cmd(esp, ESP_CMD_NULL | ESP_CMD_DMA);
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@ -257,14 +255,19 @@ static void esp_reset_esp(struct esp *esp)
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*/
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esp->max_period = ((35 * esp->ccycle) / 1000);
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if (esp->rev == FAST) {
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version = esp_read8(ESP_UID);
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family_code = (version & 0xf8) >> 3;
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if (family_code == 0x02)
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u8 family_code = ESP_FAMILY(esp_read8(ESP_UID));
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if (family_code == ESP_UID_F236) {
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esp->rev = FAS236;
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else if (family_code == 0x0a)
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} else if (family_code == ESP_UID_HME) {
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esp->rev = FASHME; /* Version is usually '5'. */
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else
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} else if (family_code == ESP_UID_FSC) {
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esp->rev = FSC;
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/* Enable Active Negation */
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esp_write8(ESP_CONFIG4_RADE, ESP_CFG4);
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} else {
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esp->rev = FAS100A;
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}
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esp->min_period = ((4 * esp->ccycle) / 1000);
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} else {
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esp->min_period = ((5 * esp->ccycle) / 1000);
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@ -308,7 +311,7 @@ static void esp_reset_esp(struct esp *esp)
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case FAS236:
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case PCSCSI:
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/* Fast 236, AM53c974 or HME */
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case FSC:
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esp_write8(esp->config2, ESP_CFG2);
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if (esp->rev == FASHME) {
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u8 cfg3 = esp->target[0].esp_config3;
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@ -2374,6 +2377,7 @@ static const char *esp_chip_names[] = {
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"ESP236",
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"FAS236",
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"AM53C974",
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"53CF9x-2",
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"FAS100A",
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"FAST",
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"FASHME",
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@ -78,12 +78,14 @@
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#define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
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#define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
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/* ESP config register 4 read-write, found only on am53c974 chips */
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#define ESP_CONFIG4_RADE 0x04 /* Active negation */
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#define ESP_CONFIG4_RAE 0x08 /* Active negation on REQ and ACK */
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#define ESP_CONFIG4_PWD 0x20 /* Reduced power feature */
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#define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 */
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#define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 */
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/* ESP config register 4 read-write */
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#define ESP_CONFIG4_BBTE 0x01 /* Back-to-back transfers (fsc) */
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#define ESP_CONGIG4_TEST 0x02 /* Transfer counter test mode (fsc) */
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#define ESP_CONFIG4_RADE 0x04 /* Active negation (am53c974/fsc) */
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#define ESP_CONFIG4_RAE 0x08 /* Act. negation REQ/ACK (am53c974) */
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#define ESP_CONFIG4_PWD 0x20 /* Reduced power feature (am53c974) */
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#define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 (am53c974) */
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#define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 (am53c974) */
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#define ESP_CONFIG_GE_12NS (0)
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#define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1)
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@ -209,10 +211,15 @@
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#define ESP_TEST_TS 0x04 /* Tristate test mode */
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/* ESP unique ID register read-only, found on fas236+fas100a only */
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#define ESP_UID_FAM 0xf8 /* ESP family bitmask */
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#define ESP_FAMILY(uid) (((uid) & ESP_UID_FAM) >> 3)
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/* Values for the ESP family bits */
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#define ESP_UID_F100A 0x00 /* ESP FAS100A */
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#define ESP_UID_F236 0x02 /* ESP FAS236 */
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#define ESP_UID_REV 0x07 /* ESP revision */
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#define ESP_UID_FAM 0xf8 /* ESP family */
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#define ESP_UID_HME 0x0a /* FAS HME */
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#define ESP_UID_FSC 0x14 /* NCR/Symbios Logic 53CF9x-2 */
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/* ESP fifo flags register read-only */
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/* Note that the following implies a 16 byte FIFO on the ESP. */
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@ -264,6 +271,7 @@ enum esp_rev {
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ESP236,
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FAS236,
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PCSCSI, /* AM53c974 */
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FSC, /* NCR/Symbios Logic 53CF9x-2 */
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FAS100A,
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FAST,
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FASHME,
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