forked from luck/tmp_suning_uos_patched
ARM: net: bpf: always use odd/even register pair
Always use an odd/even register pair for our 64-bit registers, so that we're able to use the double-word load/store instructions in the future. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
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@ -47,27 +47,27 @@
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* The callee saved registers depends on whether frame pointers are enabled.
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* With frame pointers (to be compliant with the ABI):
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*
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* high
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* original ARM_SP => +------------------+ \
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* | pc | |
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* current ARM_FP => +------------------+ } callee saved registers
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* |r4-r8,r10,fp,ip,lr| |
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* +------------------+ /
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* low
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* high
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* original ARM_SP => +--------------+ \
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* | pc | |
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* current ARM_FP => +--------------+ } callee saved registers
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* |r4-r9,fp,ip,lr| |
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* +--------------+ /
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* low
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*
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* Without frame pointers:
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*
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* high
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* original ARM_SP => +------------------+
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* | r4-r8,r10,fp,lr | callee saved registers
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* current ARM_FP => +------------------+
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* low
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* high
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* original ARM_SP => +--------------+
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* | r4-r9,fp,lr | callee saved registers
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* current ARM_FP => +--------------+
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* low
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*
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* When popping registers off the stack at the end of a BPF function, we
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* reference them via the current ARM_FP register.
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*/
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#define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
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1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R10 | \
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1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \
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1 << ARM_FP)
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#define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
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#define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC)
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@ -157,7 +157,7 @@ static const s8 bpf2a32[][2] = {
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* for constant blindings and others.
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*/
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[TMP_REG_1] = {ARM_R7, ARM_R6},
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[TMP_REG_2] = {ARM_R10, ARM_R8},
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[TMP_REG_2] = {ARM_R9, ARM_R8},
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/* Tail call count. Stored on stack scratch space. */
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[TCALL_CNT] = {STACK_OFFSET(BPF_TC_HI), STACK_OFFSET(BPF_TC_LO)},
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/* temporary register for blinding constants.
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