forked from luck/tmp_suning_uos_patched
ARM: at91: fix PM initialization for newer SoCs
Newer SoCs: at91sam9x5, at91sam9n12, sama5d3 and sama5d4 embed a DDR controller and have a different PMC status register layout than the at91sam9g45. Create another at91_sam9x5_pm_init() function to match this compatibility. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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@ -61,3 +61,23 @@ DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
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.init_machine = sam9g45_dt_device_init,
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.dt_compat = at91_9g45_board_compat,
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MACHINE_END
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static void __init sam9x5_dt_device_init(void)
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{
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at91_sam9x5_pm_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char *at91_9x5_board_compat[] __initconst = {
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"atmel,at91sam9x5",
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"atmel,at91sam9n12",
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NULL
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};
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DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
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/* Maintainer: Atmel */
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.map_io = at91_map_io,
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.init_early = at91_dt_initialize,
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.init_machine = sam9x5_dt_device_init,
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.dt_compat = at91_9x5_board_compat,
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MACHINE_END
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@ -28,7 +28,7 @@
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static void __init sama5_dt_device_init(void)
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{
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at91_sam9260_pm_init();
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at91_sam9x5_pm_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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@ -36,10 +36,12 @@ extern void at91_ioremap_matrix(u32 base_addr);
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extern void __init at91_rm9200_pm_init(void);
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extern void __init at91_sam9260_pm_init(void);
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extern void __init at91_sam9g45_pm_init(void);
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extern void __init at91_sam9x5_pm_init(void);
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#else
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void __init at91_rm9200_pm_init(void) { }
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void __init at91_sam9260_pm_init(void) { }
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void __init at91_sam9g45_pm_init(void) { }
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void __init at91_sam9x5_pm_init(void) { }
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#endif
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#endif /* _AT91_GENERIC_H */
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@ -306,3 +306,10 @@ void __init at91_sam9g45_pm_init(void)
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at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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return at91_pm_init();
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}
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void __init at91_sam9x5_pm_init(void)
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{
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at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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return at91_pm_init();
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}
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