forked from luck/tmp_suning_uos_patched
ARM: mach-shmobile: update for GIC changes.
This fixes up the SMP support to use the refactored GIC APIs. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -2,19 +2,17 @@
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* ARM Interrupt demux handler using GIC
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2010 Renesas Solutions Corp.
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* Copyright (C) 2011 Paul Mundt
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* Copyright (C) 2010 - 2011 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/assembler.h>
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#include <asm/entry-macro-multi.S>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/entry-macro-gic.S>
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =(0xf0000100)
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.endm
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arch_irq_handler shmobile_handle_irq_gic
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@ -2,15 +2,15 @@
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#define __MACH_SMP_H
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#include <asm/hardware/gic.h>
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#include <asm/smp_mpidr.h>
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/*
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* We use IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask)
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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#if defined(CONFIG_ARM_GIC)
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gic_raise_softirq(mask, 1);
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gic_raise_softirq(mask, ipi);
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#endif
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}
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#endif
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@ -252,10 +252,10 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
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void __init sh73a0_init_irq(void)
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{
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void __iomem *gic_base = __io(0xf0001000);
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void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
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gic_dist_init(0, __io(0xf0001000), 29);
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gic_cpu_init(0, __io(0xf0000100));
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gic_init(0, 29, gic_base, gic_base);
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register_intc_controller(&intcs_desc);
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@ -64,7 +64,7 @@ unsigned int __init sh73a0_get_core_count(void)
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void __cpuinit sh73a0_secondary_init(unsigned int cpu)
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{
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gic_cpu_init(0, __io(0xf0000100));
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gic_secondary_init(0);
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}
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int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
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