forked from luck/tmp_suning_uos_patched
pasemi_mac: Enable L2 caching of packet headers
Enable settings to target l2 for the first few cachelines of the packet, since we'll access them to get to the various headers. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -206,7 +206,7 @@ static int pasemi_mac_setup_rx_resources(struct net_device *dev)
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PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2));
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write_dma_reg(mac, PAS_DMA_RXCHAN_CFG(chan_id),
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PAS_DMA_RXCHAN_CFG_HBU(1));
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PAS_DMA_RXCHAN_CFG_HBU(2));
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write_dma_reg(mac, PAS_DMA_RXINT_BASEL(mac->dma_if),
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PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
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@ -215,6 +215,9 @@ static int pasemi_mac_setup_rx_resources(struct net_device *dev)
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PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
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PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
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write_dma_reg(mac, PAS_DMA_RXINT_CFG(mac->dma_if),
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PAS_DMA_RXINT_CFG_DHL(2));
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ring->next_to_fill = 0;
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ring->next_to_clean = 0;
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@ -219,6 +219,14 @@ enum {
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#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
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#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
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#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
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#define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
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#define PAS_DMA_RXINT_CFG_DHL_M 0x07000000
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#define PAS_DMA_RXINT_CFG_DHL_S 24
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#define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
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PAS_DMA_RXINT_CFG_DHL_M)
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#define PAS_DMA_RXINT_CFG_WIF 0x00000002
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#define PAS_DMA_RXINT_CFG_WIL 0x00000001
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#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
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#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
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#define PAS_DMA_RXINT_INCR_INCR_S 0
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