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[ARM] OMAP3 clock: convert dpll_data.idlest_bit to idlest_mask

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Convert struct dpll_data.idlest_bit field to idlest_mask.  Needed since
OMAP2 uses two bits for DPLL IDLEST rather than one.

While here, add the missing idlest_* fields for DPLL3.

linux-omap source commits are 25bab0f176b0a97be18a1b38153f266c3a155784
and b0f7fd17db2aaf8e6e9a2732ae3f4de0874db01c.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Paul Walmsley 2009-01-28 12:08:17 -07:00 committed by Russell King
parent b8168d1e39
commit c1bd7aaf67
3 changed files with 9 additions and 9 deletions
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6
arch/arm/mach-omap2/clock34xx.c
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@ -314,14 +314,12 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
const struct dpll_data *dd; const struct dpll_data *dd;
int i = 0; int i = 0;
int ret = -EINVAL; int ret = -EINVAL;
u32 idlest_mask;
dd = clk->dpll_data; dd = clk->dpll_data;
state <<= dd->idlest_bit; state <<= __ffs(dd->idlest_mask);
idlest_mask = 1 << dd->idlest_bit;
while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) && while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
i < MAX_DPLL_WAIT_TRIES) { i < MAX_DPLL_WAIT_TRIES) {
i++; i++;
udelay(1); udelay(1);

10
arch/arm/mach-omap2/clock34xx.h
View File

@ -266,7 +266,7 @@ static struct dpll_data dpll1_dd = {
.autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
.autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
.idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT, .max_multiplier = OMAP3_MAX_DPLL_MULT,
.max_divider = OMAP3_MAX_DPLL_DIV, .max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
@ -339,7 +339,7 @@ static struct dpll_data dpll2_dd = {
.autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
.autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
.idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT, .max_multiplier = OMAP3_MAX_DPLL_MULT,
.max_divider = OMAP3_MAX_DPLL_DIV, .max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
@ -397,6 +397,8 @@ static struct dpll_data dpll3_dd = {
.recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
.autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT, .max_multiplier = OMAP3_MAX_DPLL_MULT,
.max_divider = OMAP3_MAX_DPLL_DIV, .max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
@ -587,7 +589,7 @@ static struct dpll_data dpll4_dd = {
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
.autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT, .max_multiplier = OMAP3_MAX_DPLL_MULT,
.max_divider = OMAP3_MAX_DPLL_DIV, .max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
@ -926,7 +928,7 @@ static struct dpll_data dpll5_dd = {
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
.autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
.idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT, .max_multiplier = OMAP3_MAX_DPLL_MULT,
.max_divider = OMAP3_MAX_DPLL_DIV, .max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE

2
arch/arm/plat-omap/include/mach/clock.h
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@ -54,10 +54,10 @@ struct dpll_data {
u32 enable_mask; u32 enable_mask;
u32 autoidle_mask; u32 autoidle_mask;
u32 freqsel_mask; u32 freqsel_mask;
u32 idlest_mask;
u8 auto_recal_bit; u8 auto_recal_bit;
u8 recal_en_bit; u8 recal_en_bit;
u8 recal_st_bit; u8 recal_st_bit;
u8 idlest_bit;
# endif # endif
}; };