forked from luck/tmp_suning_uos_patched
omap: Fix gpio_request calls to happen as arch_initcall
Looks like some boards are calling gpio_request from init_irq. This will make the request_irq fail, as GPIO will be initialized as postcore_initcall. Reported-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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7b045c96cd
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c2cdaffe0b
@ -120,6 +120,15 @@ static struct resource smc91x_resources[] = {
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},
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};
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static void __init fsample_init_smc91x(void)
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{
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fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
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mdelay(50);
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fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
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H2P2_DBG_FPGA_LAN_RESET);
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mdelay(50);
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}
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static struct mtd_partition nor_partitions[] = {
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/* bootloader (U-Boot, etc) in first sector */
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{
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@ -285,6 +294,8 @@ static struct omap_board_config_kernel fsample_config[] = {
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static void __init omap_fsample_init(void)
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{
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fsample_init_smc91x();
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if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
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BUG();
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gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
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@ -312,21 +323,11 @@ static void __init omap_fsample_init(void)
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omap_register_i2c_bus(1, 100, NULL, 0);
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}
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static void __init fsample_init_smc91x(void)
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{
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fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
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mdelay(50);
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fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
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H2P2_DBG_FPGA_LAN_RESET);
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mdelay(50);
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}
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static void __init omap_fsample_init_irq(void)
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{
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omap1_init_common_hw();
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omap_init_irq();
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omap_gpio_init();
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fsample_init_smc91x();
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}
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/* Only FPGA needs to be mapped here. All others are done with ioremap */
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@ -375,7 +375,6 @@ static void __init h2_init_irq(void)
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omap1_init_common_hw();
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omap_init_irq();
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omap_gpio_init();
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h2_init_smc91x();
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}
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static struct omap_usb_config h2_usb_config __initdata = {
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@ -403,6 +402,8 @@ static struct omap_board_config_kernel h2_config[] __initdata = {
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static void __init h2_init(void)
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{
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h2_init_smc91x();
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/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
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* to address 0 by a dip switch), NAND on CS2B. The NAND driver will
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* notice whether a NAND chip is enabled at probe time.
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@ -264,6 +264,15 @@ static struct platform_device smc91x_device = {
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.resource = smc91x_resources,
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};
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static void __init h3_init_smc91x(void)
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{
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omap_cfg_reg(W15_1710_GPIO40);
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if (gpio_request(40, "SMC91x irq") < 0) {
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printk("Error requesting gpio 40 for smc91x irq\n");
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return;
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}
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}
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#define GPTIMER_BASE 0xFFFB1400
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#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
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#define GPTIMER_REGS_SIZE 0x46
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@ -376,6 +385,8 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
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static void __init h3_init(void)
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{
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h3_init_smc91x();
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/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
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* to address 0 by a dip switch), NAND on CS2B. The NAND driver will
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* notice whether a NAND chip is enabled at probe time.
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@ -422,21 +433,11 @@ static void __init h3_init(void)
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h3_mmc_init();
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}
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static void __init h3_init_smc91x(void)
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{
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omap_cfg_reg(W15_1710_GPIO40);
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if (gpio_request(40, "SMC91x irq") < 0) {
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printk("Error requesting gpio 40 for smc91x irq\n");
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return;
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}
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}
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static void __init h3_init_irq(void)
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{
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omap1_init_common_hw();
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omap_init_irq();
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omap_gpio_init();
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h3_init_smc91x();
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}
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static void __init h3_map_io(void)
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@ -296,7 +296,6 @@ static void __init innovator_init_irq(void)
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omap1510_fpga_init_irq();
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}
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#endif
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innovator_init_smc91x();
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}
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#ifdef CONFIG_ARCH_OMAP15XX
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@ -387,6 +386,8 @@ static struct omap_board_config_kernel innovator_config[] = {
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static void __init innovator_init(void)
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{
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innovator_init_smc91x();
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#ifdef CONFIG_ARCH_OMAP15XX
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if (cpu_is_omap1510()) {
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unsigned char reg;
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@ -284,8 +284,6 @@ static void __init osk_init_irq(void)
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omap1_init_common_hw();
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omap_init_irq();
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omap_gpio_init();
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osk_init_smc91x();
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osk_init_cf();
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}
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static struct omap_usb_config osk_usb_config __initdata = {
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@ -541,6 +539,9 @@ static void __init osk_init(void)
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{
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u32 l;
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osk_init_smc91x();
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osk_init_cf();
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/* Workaround for wrong CS3 (NOR flash) timing
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* There are some U-Boot versions out there which configure
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* wrong CS3 memory timings. This mainly leads to CRC
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@ -251,8 +251,19 @@ static struct omap_board_config_kernel perseus2_config[] __initdata = {
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{ OMAP_TAG_LCD, &perseus2_lcd_config },
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};
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static void __init perseus2_init_smc91x(void)
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{
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fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
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mdelay(50);
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fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
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H2P2_DBG_FPGA_LAN_RESET);
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mdelay(50);
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}
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static void __init omap_perseus2_init(void)
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{
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perseus2_init_smc91x();
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if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
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BUG();
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gpio_direction_input(P2_NAND_RB_GPIO_PIN);
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@ -280,21 +291,11 @@ static void __init omap_perseus2_init(void)
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omap_register_i2c_bus(1, 100, NULL, 0);
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}
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static void __init perseus2_init_smc91x(void)
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{
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fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
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mdelay(50);
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fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
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H2P2_DBG_FPGA_LAN_RESET);
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mdelay(50);
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}
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static void __init omap_perseus2_init_irq(void)
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{
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omap1_init_common_hw();
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omap_init_irq();
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omap_gpio_init();
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perseus2_init_smc91x();
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}
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/* Only FPGA needs to be mapped here. All others are done with ioremap */
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static struct map_desc omap_perseus2_io_desc[] __initdata = {
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@ -281,7 +281,6 @@ static void __init omap_apollon_init_irq(void)
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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omap_gpio_init();
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apollon_init_smc91x();
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}
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static void __init apollon_led_init(void)
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@ -324,6 +323,7 @@ static void __init omap_apollon_init(void)
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omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
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apollon_init_smc91x();
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apollon_led_init();
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apollon_flash_init();
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apollon_usb_init();
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@ -295,7 +295,6 @@ static void __init omap_ldp_init_irq(void)
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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omap_gpio_init();
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ldp_init_smsc911x();
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}
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static struct twl4030_usb_data ldp_usb_data = {
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@ -426,6 +425,7 @@ static struct mtd_partition ldp_nand_partitions[] = {
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static void __init omap_ldp_init(void)
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{
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omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
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ldp_init_smsc911x();
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omap_i2c_init();
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platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
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ts_gpio = 54;
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