AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

While this comes a bit later than I had wished, both patches are rather

Browse Source 
minor and touch only new drivers so I think these are still safe for
 merging.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.19 (GNU/Linux)
 
 iQIcBAABAgAGBQJQVcWAAAoJEN0jrNd/PrOhmtEP/jy9tG/aP15UM9lPacVNz89V
 LaO0jYRBZtS8A8Gi5smdjQj6nQ+ir7P06jF5YyRzA1gNkUU2pDCrdIs8Sf0KJkL0
 sJ5dRHEYuK3MNdwK2ajR6LkpFtMtGXpQtoyilwvRZWNgWCo7LMBK7k2xGYPfyF6r
 yc8/OuOyZzC83p54prW8JCun7XShgel4KYoCvYWnYzmZZ5ct0jARCgl49eJagul3
 I3nlvGfDYI4nZd9KSuWiKIor8lyW7Sk2WKfl7g9EIX+EKzsxFToQ/sRiT5mGtrTG
 gzGp31DJGVaCpdhk2/2AkjCxkh/JYNo3YqBXmQRMpGj7nkHOpQ6tz4nz1DGmJU9f
 c5ZY9rW8AUXTP0vQcW5PbxE0xnOZOVDCgkX2ZQuE7av34QPjVDsl/zDI9amx/EMC
 imyoZPk/lssVy3fuXRG4uxjmyULqk/TMnrx6pNcPOxeFr9JKs3NJVELFd6z0enrt
 6AmaaRol+XiF9IGRzai6CwwIDN8hYd9qp6e1U0bkk7bmo1D05OsUodClxX17Rr/S
 kGH6hAhhE4miWUJ2pYyfJOC1R7Tbre1G2H2wlv5jjVzNVrzasU/8NYJ8G0dYuj9z
 LCExF0QBCfZlHjW3Jn7tpLhFY0S0pSEViGckdb1kLoY3qXGHCnJhQdVon5ceWS/v
 0y7277cvE9R11TJiI2aF
 =tCsJ
 -----END PGP SIGNATURE-----

Merge tag 'for-3.6-rc6' of git://gitorious.org/linux-pwm/linux-pwm

Pull pwm fixes from Thierry Reding:
 "While this comes a bit later than I had wished, both patches are
  rather minor and touch only new drivers so I think these are still
  safe for merging."

* tag 'for-3.6-rc6' of git://gitorious.org/linux-pwm/linux-pwm:
  pwm: pwm-tiehrpwm: Fix conflicting channel period setting
  pwm: pwm-tiecap: Disable APWM mode after configure
This commit is contained in:
Linus Torvalds 2012-09-16 13:20:43 -07:00
commit c500ce38e5
2 changed files with 36 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/pwm/pwm-tiecap.c
View File

@ -100,6 +100,13 @@ static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
writel(period_cycles, pc->mmio_base + CAP3);
}
if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
reg_val = readw(pc->mmio_base + ECCTL2);
/* Disable APWM mode to put APWM output Low */
reg_val &= ~ECCTL2_APWM_MODE;
writew(reg_val, pc->mmio_base + ECCTL2);
}
pm_runtime_put_sync(pc->chip.dev);
return 0;
}

29
drivers/pwm/pwm-tiehrpwm.c
View File

@ -104,6 +104,7 @@ struct ehrpwm_pwm_chip {
struct pwm_chip chip;
unsigned int clk_rate;
void __iomem *mmio_base;
unsigned long period_cycles[NUM_PWM_CHANNEL];
};
static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
@ -210,6 +211,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
unsigned long long c;
unsigned long period_cycles, duty_cycles;
unsigned short ps_divval, tb_divval;
int i;
if (period_ns < 0 || duty_ns < 0 || period_ns > NSEC_PER_SEC)
return -ERANGE;
@ -229,6 +231,28 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
duty_cycles = (unsigned long)c;
}
/*
* Period values should be same for multiple PWM channels as IP uses
* same period register for multiple channels.
*/
for (i = 0; i < NUM_PWM_CHANNEL; i++) {
if (pc->period_cycles[i] &&
(pc->period_cycles[i] != period_cycles)) {
/*
* Allow channel to reconfigure period if no other
* channels being configured.
*/
if (i == pwm->hwpwm)
continue;
dev_err(chip->dev, "Period value conflicts with channel %d\n",
i);
return -EINVAL;
}
}
pc->period_cycles[pwm->hwpwm] = period_cycles;
/* Configure clock prescaler to support Low frequency PWM wave */
if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
&tb_divval)) {
@ -320,10 +344,15 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
if (test_bit(PWMF_ENABLED, &pwm->flags)) {
dev_warn(chip->dev, "Removing PWM device without disabling\n");
pm_runtime_put_sync(chip->dev);
}
/* set period value to zero on free */
pc->period_cycles[pwm->hwpwm] = 0;
}
static const struct pwm_ops ehrpwm_pwm_ops = {