forked from luck/tmp_suning_uos_patched
ARM: tegra20: Add Tegra Memory Controller(MC) driver
Tegra Memory Controller(MC) driver for Tegra20 Added to support MC General interrupts, mainly for IOMMU(GART). Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Hiroshi DOYU
Greg Kroah-Hartman
parent
649e6ee33f
commit
c542fb79fb
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@ -0,0 +1,16 @@
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NVIDIA Tegra20 MC(Memory Controller)
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Required properties:
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- compatible : "nvidia,tegra20-mc"
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- reg : Should contain 2 register ranges(address and length); see the
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example below. Note that the MC registers are interleaved with the
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GART registers, and hence must be represented as multiple ranges.
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- interrupts : Should contain MC General interrupt.
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Example:
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mc {
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compatible = "nvidia,tegra20-mc";
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reg = <0x7000f000 0x024
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0x7000f03c 0x3c4>;
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interrupts = <0 77 0x04>;
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};
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@ -20,6 +20,8 @@ config ARCH_TEGRA_2x_SOC
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PL310_ERRATA_769419 if CACHE_L2X0
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select CPU_FREQ_TABLE if CPU_FREQ
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select MEMORY
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select TEGRA20_MC
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help
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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@ -20,4 +20,8 @@ config TI_EMIF
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parameters and other settings during frequency, voltage and
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temperature changes
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config TEGRA20_MC
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bool
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depends on ARCH_TEGRA_2x_SOC
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endif
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@ -3,3 +3,4 @@
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#
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obj-$(CONFIG_TI_EMIF) += emif.o
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obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
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262
drivers/memory/tegra20-mc.c
Normal file
262
drivers/memory/tegra20-mc.c
Normal file
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/*
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* Tegra20 Memory Controller
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*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ratelimit.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#define DRV_NAME "tegra20-mc"
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#define MC_INTSTATUS 0x0
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#define MC_INTMASK 0x4
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#define MC_INT_ERR_SHIFT 6
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#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT)
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#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT)
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#define MC_INT_INVALID_GART_PAGE BIT(MC_INT_ERR_SHIFT + 1)
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#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2)
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#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3)
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#define MC_GART_ERROR_REQ 0x30
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#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
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#define MC_SECURITY_VIOLATION_STATUS 0x74
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#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
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#define MC_CLIENT_ID_MASK 0x3f
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#define NUM_MC_REG_BANKS 2
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struct tegra20_mc {
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void __iomem *regs[NUM_MC_REG_BANKS];
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struct device *dev;
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};
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static inline u32 mc_readl(struct tegra20_mc *mc, u32 offs)
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{
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if (offs < 0x24)
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return readl(mc->regs[0] + offs);
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BUG_ON(offs < 0x3c);
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if (offs < 0x400)
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return readl(mc->regs[1] + offs - 0x3c);
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BUG();
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}
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static inline void mc_writel(struct tegra20_mc *mc, u32 val, u32 offs)
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{
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if (offs < 0x24) {
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writel(val, mc->regs[0] + offs);
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return;
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}
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BUG_ON(offs < 0x3c);
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if (offs < 0x400) {
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writel(val, mc->regs[1] + offs - 0x3c);
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return;
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}
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BUG();
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}
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static const char * const tegra20_mc_client[] = {
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"cbr_display0a",
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"cbr_display0ab",
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"cbr_display0b",
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"cbr_display0bb",
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"cbr_display0c",
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"cbr_display0cb",
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"cbr_display1b",
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"cbr_display1bb",
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"cbr_eppup",
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"cbr_g2pr",
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"cbr_g2sr",
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"cbr_mpeunifbr",
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"cbr_viruv",
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"csr_avpcarm7r",
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"csr_displayhc",
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"csr_displayhcb",
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"csr_fdcdrd",
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"csr_g2dr",
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"csr_host1xdmar",
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"csr_host1xr",
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"csr_idxsrd",
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"csr_mpcorer",
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"csr_mpe_ipred",
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"csr_mpeamemrd",
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"csr_mpecsrd",
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"csr_ppcsahbdmar",
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"csr_ppcsahbslvr",
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"csr_texsrd",
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"csr_vdebsevr",
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"csr_vdember",
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"csr_vdemcer",
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"csr_vdetper",
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"cbw_eppu",
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"cbw_eppv",
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"cbw_eppy",
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"cbw_mpeunifbw",
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"cbw_viwsb",
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"cbw_viwu",
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"cbw_viwv",
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"cbw_viwy",
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"ccw_g2dw",
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"csw_avpcarm7w",
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"csw_fdcdwr",
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"csw_host1xw",
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"csw_ispw",
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"csw_mpcorew",
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"csw_mpecswr",
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"csw_ppcsahbdmaw",
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"csw_ppcsahbslvw",
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"csw_vdebsevw",
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"csw_vdembew",
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"csw_vdetpmw",
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};
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static void tegra20_mc_decode(struct tegra20_mc *mc, int n)
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{
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u32 addr, req;
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const char *client = "Unknown";
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int idx, cid;
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const struct reg_info {
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u32 offset;
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u32 write_bit; /* 0=READ, 1=WRITE */
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int cid_shift;
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char *message;
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} reg[] = {
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{
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.offset = MC_DECERR_EMEM_OTHERS_STATUS,
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.write_bit = 31,
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.message = "MC_DECERR",
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},
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{
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.offset = MC_GART_ERROR_REQ,
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.cid_shift = 1,
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.message = "MC_GART_ERR",
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},
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{
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.offset = MC_SECURITY_VIOLATION_STATUS,
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.write_bit = 31,
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.message = "MC_SECURITY_ERR",
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},
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};
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idx = n - MC_INT_ERR_SHIFT;
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if ((idx < 0) || (idx >= ARRAY_SIZE(reg))) {
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pr_err_ratelimited("Unknown interrupt status %08lx\n", BIT(n));
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return;
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}
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req = mc_readl(mc, reg[idx].offset);
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cid = (req >> reg[idx].cid_shift) & MC_CLIENT_ID_MASK;
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if (cid < ARRAY_SIZE(tegra20_mc_client))
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client = tegra20_mc_client[cid];
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addr = mc_readl(mc, reg[idx].offset + sizeof(u32));
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pr_err_ratelimited("%s (0x%08x): 0x%08x %s (%s %s)\n",
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reg[idx].message, req, addr, client,
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(req & BIT(reg[idx].write_bit)) ? "write" : "read",
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(reg[idx].offset == MC_SECURITY_VIOLATION_STATUS) ?
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((req & SECURITY_VIOLATION_TYPE) ?
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"carveout" : "trustzone") : "");
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}
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static const struct of_device_id tegra20_mc_of_match[] __devinitconst = {
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{ .compatible = "nvidia,tegra20-mc", },
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{},
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};
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static irqreturn_t tegra20_mc_isr(int irq, void *data)
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{
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u32 stat, mask, bit;
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struct tegra20_mc *mc = data;
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stat = mc_readl(mc, MC_INTSTATUS);
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mask = mc_readl(mc, MC_INTMASK);
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mask &= stat;
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if (!mask)
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return IRQ_NONE;
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while ((bit = ffs(mask)) != 0)
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tegra20_mc_decode(mc, bit - 1);
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mc_writel(mc, stat, MC_INTSTATUS);
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return IRQ_HANDLED;
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}
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static int __devinit tegra20_mc_probe(struct platform_device *pdev)
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{
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struct resource *irq;
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struct tegra20_mc *mc;
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int i, err;
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u32 intmask;
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mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
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if (!mc)
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return -ENOMEM;
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mc->dev = &pdev->dev;
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for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res)
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return -ENODEV;
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mc->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
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if (!mc->regs[i])
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return -EBUSY;
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}
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!irq)
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return -ENODEV;
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err = devm_request_irq(&pdev->dev, irq->start, tegra20_mc_isr,
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IRQF_SHARED, dev_name(&pdev->dev), mc);
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if (err)
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return -ENODEV;
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platform_set_drvdata(pdev, mc);
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intmask = MC_INT_INVALID_GART_PAGE |
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MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
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mc_writel(mc, intmask, MC_INTMASK);
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return 0;
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}
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static int __devexit tegra20_mc_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static struct platform_driver tegra20_mc_driver = {
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.probe = tegra20_mc_probe,
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.remove = __devexit_p(tegra20_mc_remove),
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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.of_match_table = tegra20_mc_of_match,
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},
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};
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module_platform_driver(tegra20_mc_driver);
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MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
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MODULE_DESCRIPTION("Tegra20 MC driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRV_NAME);
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