AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

V4L/DVB (7006): cx23885: Track the board clock frequency and allow overrides

Browse Source 
The cx23885/6/8 all have different clock rates, this patch allows
the core to compensate, and developers to allow vendor specific
overrides. This patches will be used by future analog video
and encoder patches.

Signed-off-by: Steven Toth <stoth@hauppauge.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Steven Toth 2008-01-10 02:24:27 -03:00 committed by Mauro Carvalho Chehab
parent 69ad6e56ba
commit c771261330
3 changed files with 25 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/media/video/cx23885/cx23885-cards.c
View File

@ -32,6 +32,8 @@
struct cx23885_board cx23885_boards[] = {
[CX23885_BOARD_UNKNOWN] = {
.name = "UNKNOWN/GENERIC",
/* Ensure safe default for unknown boards */
.clk_freq = 0,
.input = {{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = 0,

8
drivers/media/video/cx23885/cx23885-core.c
View File

@ -759,10 +759,14 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
if(dev->pci->device == 0x8880) {
dev->bridge = CX23885_BRIDGE_887;
dev->sram_channels = cx23887_sram_channels;
/* Apply a sensible clock frequency for the PCIe bridge */
dev->clk_freq = 25000000;
} else
if(dev->pci->device == 0x8852) {
dev->bridge = CX23885_BRIDGE_885;
dev->sram_channels = cx23885_sram_channels;
/* Apply a sensible clock frequency for the PCIe bridge */
dev->clk_freq = 28000000;
} else
BUG();
@ -782,6 +786,10 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
cx23885_card_list(dev);
}
/* If the user specific a clk freq override, apply it */
if (cx23885_boards[dev->board].clk_freq > 0)
dev->clk_freq = cx23885_boards[dev->board].clk_freq;
dev->pci_bus = dev->pci->bus->number;
dev->pci_slot = PCI_SLOT(dev->pci->devfn);
dev->pci_irqmask = 0x001f00;

15
drivers/media/video/cx23885/cx23885.h
View File

@ -100,6 +100,17 @@ typedef enum {
struct cx23885_board {
char *name;
port_t portb, portc;
/* Vendors can and do run the PCIe bridge at different
* clock rates, driven physically by crystals on the PCBs.
* The core has to accomodate this. This allows the user
* to add new boards with new frequencys. The value is
* expressed in Hz.
*
* The core framework will default this value based on
* current designs, but it can vary.
*/
u32 clk_freq;
struct cx23885_input input[MAX_CX23885_INPUT];
};
@ -193,6 +204,10 @@ struct cx23885_dev {
int pci_irqmask;
int hwrevision;
/* This valud is board specific and is used to configure the
* AV core so we see nice clean and stable video and audio. */
u32 clk_freq;
/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
struct cx23885_i2c i2c_bus[3];