AcoSail/kernel_optimize_test
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

Browse Source 
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Fix EV64120 and Ocelot builds by providing a plat_timer_setup().
  [MIPS] EV64120: Fix PCI interrupt allocation.
  [MIPS] Make irq number allocator generally available for fixing EV64120.
  [MIPS] EV64120: Fix timer initialization for HZ != 100.
  [MIPS] Ocelot 3: Fix MAC address detection after platform_device conversion.
  [MIPS] Ocelot C: Fix MAC address detection after platform_device conversion.
  [MIPS] SB1: On bootup only flush cache on local CPU.
  [MIPS] Ocelot 3: Fix large number of warnings.
  [MIPS] Ocelot C: Fix mapping of ioport address range.
  [MIPS] Ocelot C: Fix warning about missmatching format string.
  [MIPS] Ocelot C: fix eth registration after conversion to platform_device
  [MIPS] Ocelot C: Fix large number of warnings.
This commit is contained in:
Linus Torvalds 2006-11-06 19:53:12 -08:00
commit c836b7716a
21 changed files with 528 additions and 206 deletions
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4
arch/mips/gt64120/common/time.c
View File

@ -64,14 +64,14 @@ static irqreturn_t gt64120_irq(int irq, void *dev_id)
* as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt
* handling.
*/
void gt64120_time_init(void)
void __init plat_timer_setup(struct irqaction *irq)
{
static struct irqaction timer;
/* Disable timer first */
GT_WRITE(GT_TC_CONTROL_OFS, 0);
/* Load timer value for 100 Hz */
GT_WRITE(GT_TC3_OFS, Sys_clock / 100);
GT_WRITE(GT_TC3_OFS, Sys_clock / HZ);
/*
* Create the IRQ structure entry for the timer. Since we're too early

2
arch/mips/gt64120/ev64120/setup.c
View File

@ -68,7 +68,6 @@ unsigned long __init prom_free_prom_memory(void)
* Initializes basic routines and structures pointers, memory size (as
* given by the bios and saves the command line.
*/
extern void gt64120_time_init(void);
void __init plat_mem_setup(void)
{
@ -76,7 +75,6 @@ void __init plat_mem_setup(void)
_machine_halt = galileo_machine_halt;
pm_power_off = galileo_machine_power_off;
board_time_init = gt64120_time_init;
set_io_port_base(KSEG1);
}

3
arch/mips/gt64120/momenco_ocelot/setup.c
View File

@ -70,7 +70,6 @@ extern void momenco_ocelot_restart(char *command);
extern void momenco_ocelot_halt(void);
extern void momenco_ocelot_power_off(void);
extern void gt64120_time_init(void);
extern void momenco_ocelot_irq_setup(void);
static char reset_reason;
@ -156,8 +155,6 @@ void __init plat_mem_setup(void)
void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
unsigned int tmpword;
board_time_init = gt64120_time_init;
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
pm_power_off = momenco_ocelot_power_off;

42
arch/mips/kernel/irq.c
View File

@ -26,6 +26,48 @@
#include <asm/system.h>
#include <asm/uaccess.h>
static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
int __devinit allocate_irqno(void)
{
int irq;
again:
irq = find_first_zero_bit(irq_map, NR_IRQS);
if (irq >= NR_IRQS)
return -ENOSPC;
if (test_and_set_bit(irq, irq_map))
goto again;
return irq;
}
EXPORT_SYMBOL_GPL(allocate_irqno);
/*
* Allocate the 16 legacy interrupts for i8259 devices. This happens early
* in the kernel initialization so treating allocation failure as BUG() is
* ok.
*/
void __init alloc_legacy_irqno(void)
{
int i;
for (i = 0; i <= 16; i++)
BUG_ON(test_and_set_bit(i, irq_map));
}
void __devinit free_irqno(unsigned int irq)
{
smp_mb__before_clear_bit();
clear_bit(irq, irq_map);
smp_mb__after_clear_bit();
}
EXPORT_SYMBOL_GPL(free_irqno);
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
* each architecture has to answer this themselves.

2
arch/mips/mm/c-sb1.c
View File

@ -505,5 +505,5 @@ void sb1_cache_init(void)
:
: "memory");
flush_cache_all();
local_sb1___flush_cache_all();
}

2
arch/mips/momentum/ocelot_3/Makefile
View File

@ -5,4 +5,4 @@
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
obj-y += irq.o prom.o reset.o setup.o
obj-y += irq.o platform.o prom.o reset.o setup.o

6
arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
View File

@ -51,7 +51,9 @@
extern unsigned long ocelot_fpga_base;
#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y)
#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x)
#define __FPGA_REG_TO_ADDR(reg) \
((void *) ocelot_fpga_base + OCELOT_3_REG_##reg)
#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
#endif

235
arch/mips/momentum/ocelot_3/platform.c Normal file
View File

@ -0,0 +1,235 @@
#include <linux/delay.h>
#include <linux/if_ether.h>
#include <linux/ioport.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
#include "ocelot_3_fpga.h"
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
.name = "ethernet shared base",
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
MV643XX_ETH_SHARED_REGS_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv643xx_eth_shared_device = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
.resource = mv643xx_eth_shared_resources,
};
#define MV_SRAM_BASE 0xfe000000UL
#define MV_SRAM_SIZE (256 * 1024)
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
#define MV64x60_IRQ_ETH_0 48
#define MV64x60_IRQ_ETH_1 49
#define MV64x60_IRQ_ETH_2 50
#ifdef CONFIG_MV643XX_ETH_0
static struct resource mv64x60_eth0_resources[] = {
[0] = {
.name = "eth0 irq",
.start = MV64x60_IRQ_ETH_0,
.end = MV64x60_IRQ_ETH_0,
.flags = IORESOURCE_IRQ,
},
};
static char eth0_mac_addr[ETH_ALEN];
static struct mv643xx_eth_platform_data eth0_pd = {
.mac_addr = eth0_mac_addr,
.tx_sram_addr = MV_SRAM_BASE_ETH0,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
.resource = mv64x60_eth0_resources,
.dev = {
.platform_data = &eth0_pd,
},
};
#endif /* CONFIG_MV643XX_ETH_0 */
#ifdef CONFIG_MV643XX_ETH_1
static struct resource mv64x60_eth1_resources[] = {
[0] = {
.name = "eth1 irq",
.start = MV64x60_IRQ_ETH_1,
.end = MV64x60_IRQ_ETH_1,
.flags = IORESOURCE_IRQ,
},
};
static char eth1_mac_addr[ETH_ALEN];
static struct mv643xx_eth_platform_data eth1_pd = {
.mac_addr = eth1_mac_addr,
.tx_sram_addr = MV_SRAM_BASE_ETH1,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
.resource = mv64x60_eth1_resources,
.dev = {
.platform_data = &eth1_pd,
},
};
#endif /* CONFIG_MV643XX_ETH_1 */
#ifdef CONFIG_MV643XX_ETH_2
static struct resource mv64x60_eth2_resources[] = {
[0] = {
.name = "eth2 irq",
.start = MV64x60_IRQ_ETH_2,
.end = MV64x60_IRQ_ETH_2,
.flags = IORESOURCE_IRQ,
},
};
static char eth2_mac_addr[ETH_ALEN];
static struct mv643xx_eth_platform_data eth2_pd = {
.mac_addr = eth2_mac_addr,
};
static struct platform_device eth2_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
.resource = mv64x60_eth2_resources,
.dev = {
.platform_data = &eth2_pd,
},
};
#endif /* CONFIG_MV643XX_ETH_2 */
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
&mv643xx_eth_shared_device,
#ifdef CONFIG_MV643XX_ETH_0
&eth0_device,
#endif
#ifdef CONFIG_MV643XX_ETH_1
&eth1_device,
#endif
#ifdef CONFIG_MV643XX_ETH_2
&eth2_device,
#endif
};
static u8 __init exchange_bit(u8 val, u8 cs)
{
/* place the data */
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
udelay(1);
/* turn the clock on */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
udelay(1);
/* turn the clock off and read-strobe */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
}
static void __init get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
/*
* Copy and increment ethernet MAC address by a small value.
*
* This is useful for systems where the only one MAC address is stored in
* non-volatile memory for multiple ports.
*/
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
unsigned int add)
{
int i;
BUG_ON(add >= 256);
for (i = ETH_ALEN; i >= 0; i--) {
dst[i] = src[i] + add;
add = dst[i] < src[i]; /* compute carry */
}
WARN_ON(add);
}
static int __init mv643xx_eth_add_pds(void)
{
unsigned char mac[ETH_ALEN];
int ret;
get_mac(mac);
#ifdef CONFIG_MV643XX_ETH_0
eth_mac_add(eth1_mac_addr, mac, 0);
#endif
#ifdef CONFIG_MV643XX_ETH_1
eth_mac_add(eth1_mac_addr, mac, 1);
#endif
#ifdef CONFIG_MV643XX_ETH_2
eth_mac_add(eth2_mac_addr, mac, 2);
#endif
ret = platform_add_devices(mv643xx_eth_pd_devs,
ARRAY_SIZE(mv643xx_eth_pd_devs));
return ret;
}
device_initcall(mv643xx_eth_add_pds);
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */

58
arch/mips/momentum/ocelot_3/prom.c
View File

@ -34,64 +34,11 @@ struct callvectors* debug_vectors;
extern unsigned long marvell_base;
extern unsigned long cpu_clock;
#ifdef CONFIG_MV643XX_ETH
extern unsigned char prom_mac_addr_base[6];
#endif
const char *get_system_type(void)
{
return "Momentum Ocelot-3";
}
#ifdef CONFIG_MV643XX_ETH
void burn_clocks(void)
{
int i;
/* this loop should burn at least 1us -- this should be plenty */
for (i = 0; i < 0x10000; i++)
;
}
u8 exchange_bit(u8 val, u8 cs)
{
/* place the data */
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
burn_clocks();
/* turn the clock on */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
burn_clocks();
/* turn the clock off and read-strobe */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
}
void get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
#endif
#ifdef CONFIG_64BIT
unsigned long signext(unsigned long addr)
@ -228,11 +175,6 @@ void __init prom_init(void)
mips_machgroup = MACH_GROUP_MOMENCO;
mips_machtype = MACH_MOMENCO_OCELOT_3;
#ifdef CONFIG_MV643XX_ETH
/* get the base MAC address for on-board ethernet ports */
get_mac(prom_mac_addr_base);
#endif
#ifndef CONFIG_64BIT
debug_vectors->printf("Booting Linux kernel...\n");
#endif

2
arch/mips/momentum/ocelot_3/setup.c
View File

@ -4,7 +4,7 @@
* BRIEF MODULE DESCRIPTION
* Momentum Computer Ocelot-3 board dependent boot routines
*
* Copyright (C) 1996, 1997, 01, 05 Ralf Baechle
* Copyright (C) 1996, 1997, 01, 05 - 06 Ralf Baechle
* Copyright (C) 2000 RidgeRun, Inc.
* Copyright (C) 2001 Red Hat, Inc.
* Copyright (C) 2002 Momentum Computer

2
arch/mips/momentum/ocelot_c/Makefile
View File

@ -2,7 +2,7 @@
# Makefile for Momentum Computer's Ocelot-C and -CS boards.
#
obj-y += cpci-irq.o irq.o prom.o reset.o \
obj-y += cpci-irq.o irq.o platform.o prom.o reset.o \
setup.o uart-irq.o
obj-$(CONFIG_KGDB) += dbg_io.o

6
arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
View File

@ -53,7 +53,9 @@
#define OCELOT_C_REG_INTSET 0xe
#define OCELOT_C_REG_INTCLR 0xf
#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y)
#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x)
#define __FPGA_REG_TO_ADDR(reg) \
((void *) OCELOT_C_CS0_ADDR + OCELOT_C_REG_##reg)
#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
#endif

201
arch/mips/momentum/ocelot_c/platform.c Normal file
View File

@ -0,0 +1,201 @@
#include <linux/delay.h>
#include <linux/if_ether.h>
#include <linux/ioport.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
#include "ocelot_c_fpga.h"
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
.name = "ethernet shared base",
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
MV643XX_ETH_SHARED_REGS_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv643xx_eth_shared_device = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
.resource = mv643xx_eth_shared_resources,
};
#define MV_SRAM_BASE 0xfe000000UL
#define MV_SRAM_SIZE (256 * 1024)
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
#define MV64x60_IRQ_ETH_0 48
#define MV64x60_IRQ_ETH_1 49
#ifdef CONFIG_MV643XX_ETH_0
static struct resource mv64x60_eth0_resources[] = {
[0] = {
.name = "eth0 irq",
.start = MV64x60_IRQ_ETH_0,
.end = MV64x60_IRQ_ETH_0,
.flags = IORESOURCE_IRQ,
},
};
static char eth0_mac_addr[ETH_ALEN];
static struct mv643xx_eth_platform_data eth0_pd = {
.mac_addr = eth0_mac_addr,
.tx_sram_addr = MV_SRAM_BASE_ETH0,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
.resource = mv64x60_eth0_resources,
.dev = {
.platform_data = &eth0_pd,
},
};
#endif /* CONFIG_MV643XX_ETH_0 */
#ifdef CONFIG_MV643XX_ETH_1
static struct resource mv64x60_eth1_resources[] = {
[0] = {
.name = "eth1 irq",
.start = MV64x60_IRQ_ETH_1,
.end = MV64x60_IRQ_ETH_1,
.flags = IORESOURCE_IRQ,
},
};
static char eth1_mac_addr[ETH_ALEN];
static struct mv643xx_eth_platform_data eth1_pd = {
.mac_addr = eth1_mac_addr,
.tx_sram_addr = MV_SRAM_BASE_ETH1,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
.resource = mv64x60_eth1_resources,
.dev = {
.platform_data = &eth1_pd,
},
};
#endif /* CONFIG_MV643XX_ETH_1 */
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
&mv643xx_eth_shared_device,
#ifdef CONFIG_MV643XX_ETH_0
&eth0_device,
#endif
#ifdef CONFIG_MV643XX_ETH_1
&eth1_device,
#endif
/* The third port is not wired up on the Ocelot C */
};
static u8 __init exchange_bit(u8 val, u8 cs)
{
/* place the data */
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
udelay(1);
/* turn the clock on */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
udelay(1);
/* turn the clock off and read-strobe */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
}
static void __init get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
/*
* Copy and increment ethernet MAC address by a small value.
*
* This is useful for systems where the only one MAC address is stored in
* non-volatile memory for multiple ports.
*/
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
unsigned int add)
{
int i;
BUG_ON(add >= 256);
for (i = ETH_ALEN; i >= 0; i--) {
dst[i] = src[i] + add;
add = dst[i] < src[i]; /* compute carry */
}
WARN_ON(add);
}
static int __init mv643xx_eth_add_pds(void)
{
unsigned char mac[ETH_ALEN];
int ret;
get_mac(mac);
#ifdef CONFIG_MV643XX_ETH_0
eth_mac_add(eth1_mac_addr, mac, 0);
#endif
#ifdef CONFIG_MV643XX_ETH_1
eth_mac_add(eth1_mac_addr, mac, 1);
#endif
ret = platform_add_devices(mv643xx_eth_pd_devs,
ARRAY_SIZE(mv643xx_eth_pd_devs));
return ret;
}
device_initcall(mv643xx_eth_add_pds);
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */

60
arch/mips/momentum/ocelot_c/prom.c
View File

@ -29,11 +29,7 @@
struct callvectors* debug_vectors;
extern unsigned long marvell_base;
extern unsigned long cpu_clock;
#ifdef CONFIG_MV643XX_ETH
extern unsigned char prom_mac_addr_base[6];
#endif
extern unsigned int cpu_clock;
const char *get_system_type(void)
{
@ -44,55 +40,6 @@ const char *get_system_type(void)
#endif
}
#ifdef CONFIG_MV643XX_ETH
static void burn_clocks(void)
{
int i;
/* this loop should burn at least 1us -- this should be plenty */
for (i = 0; i < 0x10000; i++)
;
}
static u8 exchange_bit(u8 val, u8 cs)
{
/* place the data */
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
burn_clocks();
/* turn the clock on */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
burn_clocks();
/* turn the clock off and read-strobe */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
}
void get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
#endif
#ifdef CONFIG_64BIT
unsigned long signext(unsigned long addr)
@ -226,11 +173,6 @@ void __init prom_init(void)
mips_machgroup = MACH_GROUP_MOMENCO;
mips_machtype = MACH_MOMENCO_OCELOT_C;
#ifdef CONFIG_MV643XX_ETH
/* get the base MAC address for on-board ethernet ports */
get_mac(prom_mac_addr_base);
#endif
#ifndef CONFIG_64BIT
debug_vectors->printf("Booting Linux kernel...\n");
#endif

23
arch/mips/momentum/ocelot_c/setup.c
View File

@ -69,8 +69,7 @@
#include "ocelot_c_fpga.h"
unsigned long marvell_base;
extern unsigned long mv64340_sram_base;
unsigned long cpu_clock;
unsigned int cpu_clock;
/* These functions are used for rebooting or halting the machine*/
extern void momenco_ocelot_restart(char *command);
@ -119,7 +118,6 @@ void PMON_v2_setup(void)
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
marvell_base = 0xfffffffff4000000;
mv64340_sram_base = 0xfffffffffe000000;
#else
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
@ -129,7 +127,6 @@ void PMON_v2_setup(void)
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
marvell_base = 0xf4000000;
mv64340_sram_base = 0xfe000000;
#endif
}
@ -346,22 +343,20 @@ void __init plat_mem_setup(void)
}
}
#ifndef CONFIG_64BIT
/* This needs to be one of the first initcalls, because no I/O port access
can work before this */
/*
* This needs to be one of the first initcalls, because no I/O port access
* can work before this
*/
static int io_base_ioremap(void)
{
/* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
void *io_remap_range = ioremap(0xc0000000, 0x30000000);
void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
if (!io_remap_range) {
if (!io_remap_range)
panic("Could not ioremap I/O port range");
}
printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
set_io_port_base(io_remap_range - 0xc0000000);
set_io_port_base((unsigned long) io_remap_range);
return 0;
}
module_init(io_base_ioremap);
#endif

2
arch/mips/pci/Makefile
View File

@ -26,7 +26,7 @@ obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o
obj-$(CONFIG_MIPS_EV64120) += pci-ev64120.o
obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o

34
arch/mips/pci/fixup-ev64120.c
View File

@ -1,34 +0,0 @@
#include <linux/pci.h>
#include <linux/init.h>
int pci_range_ck(unsigned char bus, unsigned char dev)
{
if (((bus == 0) || (bus == 1)) && (dev >= 6) && (dev <= 8))
return 0;
return -1;
}
/*
* After detecting all agents over the PCI , this function is called
* in order to give an interrupt number for each PCI device starting
* from IRQ 20. It does also enables master for each device.
*/
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
unsigned int irq = 20;
struct pci_bus *current_bus = bus;
struct pci_dev *dev;
struct list_head *devices_link;
list_for_each(devices_link, &(current_bus->devices)) {
dev = pci_dev_b(devices_link);
if (dev != NULL) {
dev->irq = irq++;
/* Assign an interrupt number for the device */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
pcibios_set_master(dev);
}
}
}

21
arch/mips/pci/pci-ev64120.c Normal file
View File

@ -0,0 +1,21 @@
#include <linux/pci.h>
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
if (!pin)
return 0;
irq = allocate_irqno();
if (irq < 0)
return 0;
return irq;
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}

23
arch/mips/sgi-ip27/ip27-irq.c
View File

@ -354,29 +354,6 @@ static struct irq_chip bridge_irq_type = {
.end = end_bridge_irq,
};
static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
int allocate_irqno(void)
{
int irq;
again:
irq = find_first_zero_bit(irq_map, NR_IRQS);
if (irq >= NR_IRQS)
return -ENOSPC;
if (test_and_set_bit(irq, irq_map))
goto again;
return irq;
}
void free_irqno(unsigned int irq)
{
clear_bit(irq, irq_map);
}
void __devinit register_bridge_irq(unsigned int irq)
{
irq_desc[irq].status = IRQ_DISABLED;

2
arch/mips/sgi-ip27/ip27-timer.c
View File

@ -214,8 +214,6 @@ static struct irqaction rt_irqaction = {
.name = "timer"
};
extern int allocate_irqno(void);
void __init plat_timer_setup(struct irqaction *irq)
{
int irqno = allocate_irqno();

4
include/asm-mips/irq.h
View File

@ -74,4 +74,8 @@ extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
unsigned long hwmask);
#endif /* CONFIG_MIPS_MT_SMTC */
extern int allocate_irqno(void);
extern void alloc_legacy_irqno(void);
extern void free_irqno(unsigned int irq);
#endif /* _ASM_IRQ_H */